ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<ngcortes>
NB: intel mesa ci is back online (looks like it was a network outage). Thank you for your patience
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<DemiMarie>
<robclark> "it's really just some sqe code..." <- Time for some clean room RE?
<robclark>
I mean, for anything other than dev boards we wouldn't be able to sign our own zap fw.. OTOH upstream only uses it to take the gpu out of secure state on when taking gpu out of power-collapse (suspend).. a stub zap fw that didn't really do anything might be useful for some limited cases (ie. CI on dev boards where we didn't want to redistribute the official fw as part of the CI infra)
<robclark>
writing our own sqe.fw would be more useful.. but also a big time suck and there are plenty of more important things to do
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<mareko>
tarceri: it's a new pass called nir_opt_varyings using load_input/store_output, yes it works across stages, the NIR variables are not used by anything except nir_build_program_resource_list; for linking we can just get the varying usage from shader_info if the only use is to fail linking if there are too many
<mareko>
I have about a half of it done, I'm hoping to optimize things like interp(x) + interp(y) ---> interp(x + y), for example
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<mareko>
it'll be a sick pass
<zmike>
π₯
<tarceri>
sounds good mareko :)
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<dj-death>
what notations would people use if we wanted to extend the max vector length from 16 to 32? :)
<dj-death>
would run out of letters at 26
<dj-death>
use capital letters? ;)
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<dj-death>
cwabbott: I see you're awake :)
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<cwabbott>
dj-death: well, I'm on european timezone so this is a normal time to be awake :)
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<dj-death>
ah :)
<dj-death>
could use digits too
<dj-death>
don't know
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<dj-death>
DG2 is able to load up to 64 dwords
<dj-death>
not sure we want to go up to that
<dj-death>
but 32 would be nice
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<glehmann>
dj-death: couldn't you use a 64bit vec16 for 32 dwords?
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<glehmann>
or maybe not because bit sizes are weird on intel iirc
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<dj-death>
glehmann: 64bit data should work on DG2, but if I can avoid some massaging of the data types, it's nicer tbh
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<alyssa>
zmike: zink really needs to get on the load_input/store_output train
<alyssa>
choo choo
<alyssa>
("isn't that impossible though?" "CHOO CHOO!")
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<ccr>
"all aboard the train!"
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<zmike>
patches welcome
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<derRichard>
i have a question on mipi dsi. my panel enables power supply in ->prepare() and does mipi_dsi_dcs_exit_sleep_mode() in ->enable(), but on the scope i see that display data is sent via mipi dsi *before* ->prepare(). the data sheet of my display requires that power has to be enabled first. how can i control this?
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<DavidHeidelberg[m]>
anholt: is these lines "deqp-vk[534]: segfault at 24 ip 0000556d8da75f42 sp 00007ffeea9cd920 error 4 in deqp-vk[556d8cedd000+35b3000] likely on CPU 2 (core 1, socket 0)" considered as OK or serious issue with HW/driver?
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<frieder>
derRichard: I think this depends on how your DSI controller driver is implemented. If it is a bridge driver things should work as described here:
<frieder>
derRichard: You might need to use the recently added prepare_prev_first flag in your panel driver.
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<karolherbst_>
davinci resolve runs on mesa :3
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<HdkR>
karolherbst_: Does it require OpenCL or something?
<karolherbst_>
yes
<HdkR>
Wacky
<karolherbst_>
it requires a few things even
<karolherbst_>
image2d_from_buffer
<karolherbst_>
gl_sharing
<karolherbst_>
proper workgroup info
<karolherbst_>
so it depends on 3 MRs atm :D
<HdkR>
whoa
<karolherbst_>
but it does run
<karolherbst_>
and the big thing is: apparnetly it doens't work on Intels official CL runtime :D
<karolherbst_>
but yeah
<karolherbst_>
it uses all those crazy features
<HdkR>
Just replace the proprietary Intel runtime with Rusticl, sounds good to me
<HdkR>
So how soon until I can run Davinci Resolve on my Snapdragon laptop? :P
<karolherbst_>
:D
<karolherbst_>
hopefully I can merge some stuff soon
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<HdkR>
nice nice nice
<anholt_>
DavidHeidelberg[m]: segfaulting in deqp is probably just a driver bug. you probably have some xfails with crashes?
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<karolherbst_>
yeah.. the image2d_from_buffer stuff is good to go, so with that merged there are just 2 MRs left, and I might remove the radeonsi commit from one so I can merge it :)
<karolherbst_>
the gl_sharing one might still require some work tho
<HdkR>
Well it works in my emulator, but I just don't have a real GPU apparently :P
<karolherbst_>
heh
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<MrCooper>
karolherbst_: rusticl with radeonsi when though :P
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<karolherbst_>
heh
<karolherbst_>
hopefully this month
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<DavidHeidelberg[m]>
anholt_: I'll check xfails (in ~ 2hrs), but I'm afraid I didn't see anything in artifacts
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<airlied>
anholt_, zmike : is there a writeup on cmd buffer usage diffs between angle/zink?
<anholt_>
I've talked about it in this chan or #zink before, I forget where
<airlied>
beyond the queries?
<airlied>
like you make it sound like a fundamental design problem in zink
<airlied>
I don't remember hearing that conversation at all
<anholt_>
basically: angle records its commands in a thing called a secondary, which is not actually a vk secondary. This lets it go in and edit renderpass stuff as it catches buffer invalidates, late clears, etc. Only at submit time does that secondary get turned into a vk cmdbuf
<airlied>
ah okay that is pretty fundamental, thanks!
<anholt_>
they don't love the overhead of doing so, but had to. so there's been some discussion of "how much could we move the late fixups to the vk driver, by emitting commands for like "whoops, actually make my load op a dont_care instead of a load for this render pass, thanks"
<zmike>
this is what tc renderpass optimizing fixes in zink
<anholt_>
zmike: so, do you process arbitrary amounts of calls looking for the end of the rp in tc?
<zmike>
yeah something like that
<zmike>
all the attachment usage/invalidation is accumulated for use at the start of the renderpass
<zmike>
the overhead is pretty minimal, like 5% in the base drawoverhead case and otherwise unnoticeable
<anholt_>
hohoho. If this testing is to be trusted, with the 16-bit fix, and having switched my test device to adl, zink is -18% perf of iris on android, and angle is -22% of iris. couple of big wins for zink (probably some of the fixes we've written), but also a bug chunk of angle sucking more on this hw for reasons I haven't investigated.
<zmike>
oooo
<anholt_>
this is my first time seeing zink pull ahead of angle in any set of tests, though. so pretty cool.
<zmike>
itshappening.gif
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<DemiMarie>
How does Panfrost compare to the ARM Mali driver in terms of performance and features?
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<daniels>
I mean, it's +/- 40% depending on which usecase or benchmark you select
<daniels>
same with all drivers
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<DemiMarie>
emersion: are you saying it was a bad question? daniels: what about correctness (e.g. Khronos CTS)?
<emersion>
no, it's not a bad question
<daniels>
DemiMarie: on most generations it's every bit as conformant as the proprietary driver. it's an unanswerable question though, as is 'is Windows or Linux faster on my laptop?': Panfrost optimises for the usecases that are important to our userbase within the limitations of our driver architecture, and the proprietary driver does the same within theirs. there's no universally correct answer.
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<DemiMarie>
emersion: βyesβ is not really a *useful* answer, at least not without additional context. daniels: the reason I asked is that I was told that only the Mali and Adreno drivers have passed the Android CTS.
<emersion>
was more of a joke than anything else
<emersion>
nobody here will tell you that the blob is better ;)
<daniels>
DemiMarie: the Android CTS is different to the GL/VK/etc CTS; it's also not possible to give an answer generically for Panfrost because the Android CTS tests a bunch of platform-integration stuff which needs to be done for each SoC family
<javierm>
daniels: that video is so funny :D
<daniels>
DemiMarie: the Panfrost CTS pass results are visible within CI, as well as by going to khronos.org and looking for the list of conformant products
<DemiMarie>
daniels: What kind of stuff?
<daniels>
javierm: the full one is even better, as you can see his translator sweating profusely
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<daniels>
DemiMarie: display, gralloc, etc
<DemiMarie>
daniels: I see. So this isnβt a Panfrost limitation then.
<javierm>
daniels: LOL
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<daniels>
DemiMarie: not specifically, no
<FireBurn>
zmike: Have you done much testing with zink on any PRIME devices?
<zmike>
all my devices are prime πͺ πͺ πͺ
<zmike>
but also no
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<FireBurn>
I've an AMD/AMD setup here, and I'm seeing very similar FPS on the Unigene benchmarks for radeonsi and zink, but I notice that playing it under zink "feels" sluggish
<HdkR>
Throw some Mangohud at it to see 1% and 0.1% lows and see if it is stuttering more? :)
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<zmike>
yeah you might not be getting the right device since zink does its own ordering
<zmike>
see also the 50 tickets open about it
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<robclark>
DemiMarie: that is not true, freedreno (and intel and amd) all regularly pass android CTS.. any CTS fails are release blockers for ChromeOS
<FireBurn>
zmike: Pretty sure it's rendering to the correct one, as the APU is no where near as fast as the 6800M, just wondered if it was the copy to the APU that was "slow"
<zmike>
uhh
<FireBurn>
There were quite a few improvements to radv and radeonsi to use SDMA to copy the image to allow the render to get back to rendering
<zmike>
no idea tbh
<zmike>
I have no such machine, so it's not something I can examine
<FireBurn>
No worries, hopefully AMD decide to gift you with one of their AMD Advantage laptops in the future, they really are killer :D
<zmike>
intriguing
<zmike>
maybe I'll get one
<zmike>
I need a rival for my old intel icelake
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<FireBurn>
I previously has Intel/AMD
<FireBurn>
and Intel/AMD before that
<FireBurn>
Anything to avoid nVidea
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