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<konradybcio> bamse what would you say for a common qcom,aoss-qmp compatible? there are already 6 different ones without any different .data
<anholt_> konradybcio: hoping you might have some clues on db820c failures on 5.14-rc3. two of them so far.
<anholt_> 1) fail to boot with:
<anholt_> [ 7.713675] dwc3-qcom 6af8800.usb: IRQ dp_hs_phy_irq not found
<anholt_> [ 7.792084] phy phy-7411000.phy.5: phy init failed --> -16
<anholt_> [ 7.788177] phy phy-7411000.phy.5: QUSB2PHY pll lock failed: status reg = 0
<anholt_> [ 7.714541] dwc3-qcom 6af8800.usb: IRQ dm_hs_phy_irq not found
<anholt_> [ 7.794834] dwc3 6a00000.dwc3: error -EBUSY: failed to initialize core
<anholt_> after a short stall, the board reboots.
<anholt_> 2) [ 62.217128] thermal thermal_zone3: cpu3-thermal: critical temperature reached, shutting down
<anholt_> [ 62.217176] reboot: HARDWARE PROTECTION shutdown (Temperature too high)
<anholt_> (I'm suspecting the CPU OPP stuff, which was what I was hoping to test out since our db820cs are so shockingly slow currently)
<konradybcio> 1) I don't have any immediate ideas
<konradybcio> 2) yeah most likely, but Bjorn also had some stability issues, probably concerning lack of CPR and/or too low cpu voltage (which isn't necessarily mutually exclusive)
<konradybcio> https://patchwork.kernel.org/project/linux-arm-msm/list/?series=509577 this series implements most of the things needed for CPR but you are not supposed to run it on 8996 as this soc needs a special silicon aging algorithm on top of that, you may get bogus values
<konradybcio> if you don't care about thermals, you can pin the VDD_APC0/1 regulators to their max values to ensure CPUs get enough juice
<anholt_> well, if I'm getting critical temp shutdowns, thermals are kind of important to me :)
<konradybcio> fair :p
<konradybcio> you can also try shaving off all frequencies from the OPP tables except the lowest one or so
<konradybcio> also, I think that all aoss_qmp: size fields in reg=<> are wrong on sm8[1/2/3]50
<anholt_> before the OPP, what would my CPUs have been running at? I haven't found a way to get at the current clock.
<konradybcio> anholt_: at the frequency your bootloader set them to, you can add clk_ignore_unused and revert the "add opp blabla" patch and check in /sys/kernel/debug/clk/thenameoftheclock/clk_rate
<anholt_> thanks