<narmstrong>
Marijn[m]: yes the rate should be reduced by 3 when used with dsc
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<Marijn[m]>
narmstrong: I don't recall seeing the code in dsi_host that takes care of that... Are you looking into this?
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<lumag>
narmstrong, I don't see the corresponding code in downstream too, to lower the clocks in DSI case
<lumag>
*DSC
<Marijn[m]>
lumag: me neither but it's rather convoluted. Downstream hardcodes it in DT and it's only marginally lower than what mainline calculates for the same panel/device...
<Marijn[m]>
Perhaps we should compare clk_summary and/or debugcc and make sure? Or are these devices having a far too high clock all the time, wasting energy (but perhaps improving latency...)?
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<narmstrong>
Marijn[m]: lumag: it's handled via dsi_h_active_dce() in dsi_panel_calc_dsi_transfer_time()
<narmstrong>
dsi_h_active_dce() returns pclk_per_line which is DIV_ROUND_UP(total_bytes_per_intf, 3) which is equal to hdisplay/3 when bpp is 24
<narmstrong>
dsi_h_total_dce() also retursn the htotal with hdisplay/3 for video mode
<Marijn[m]>
narmstrong: saw that but dismissed it as "seen that code somewhere during DSC patch review, so we must already handle it" without further checking if h_active propagates into clock calculations anywhere
<narmstrong>
we clearly don't have `dsi_panel_calc_dsi_transfer_time()` equivalent in upstream
<narmstrong>
what we have in upstream is dividing hdisplay/3 when setting the video/cmd mode timings, but not the clk
<narmstrong>
`Divide the display by 3 but keep back/font porch and pulse width same` in dsi_timing_setup()
<Marijn[m]>
narmstrong: right, yes, I've seen and modified the code that writes this value into a register
<Marijn[m]>
Are you onto a patch to apply it to the clk / transfer time as well?
<narmstrong>
Marijn[m]: the next step is to try once I have a calculation that works
<Marijn[m]>
narmstrong: looking forward to that, or will try my own hand at it when back home otherwise
<vknecht[m]>
aka_: afaik from recent discussion in #_oftc_#aosp-developers:matrix.org mm-radio is not complete and parts have to be "emulated" just to show network icon. with QRTR modem one could follow up on Caleb's qrild (aospm repo)
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<lumag>
anybody having experience with pwm setup on pm8994/8996 ?
<lumag>
konradybcio, Marijn[m] ^
<konradybcio>
no
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<Marijn[m]>
lumag: listing two socs I don't own ;)
<lumag>
:D
<Marijn[m]>
lumag: is Bjorn's LPG driver applicable to these?
<lumag>
Marijn[m], yes, but I'm stuck with parameters / pinctrl
<lumag>
bamse, ^^
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<Marijn[m]>
lumag: parameters as in, no idea what to fill in inside the driver structure?
<lumag>
Marijn[m], no, qcom,dtest, function etc.
<Marijn[m]>
lumag: hmm, I recall somehow finding definitive info downstream whether or not to use dtest on pm660l
<Marijn[m]>
lumag: unfortunately I don't recall having any pinctrl...?
<lumag>
Marijn[m], ack, thanks anyway
* lumag
is trying to enable the db410c panel kit on db820c
* Marijn[m]
is trying to enable DSC panels on sm8123450 devices, and submit the patches for sm6125
<lumag>
Tooniis[m], maybe you remember details? I'm trying to get PWM output on pm8996 GPIO5
<lumag>
But config from your xiaomi dtsi doesn't seem to work
<Marijn[m]>
Any idea when the first 8550-based boards/devices start coming out? I haven't kept up at all :)
<Marijn[m]>
Seen the OP11 at least
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<lumag>
Marijn[m], I'm waiting for Xiaomi to provide 8550-based phone. Or for updating their DTS repo :D
<Marijn[m]>
lumag: lol :D
<lumag>
ok, by manually setting gpio666 to out / 1 I got the image.
<konradybcio>
that's a lot of gpios
<lumag>
ok, fixed it now :-)
<lumag>
Got simultaneous HDMI and DSI :-)
<lumag>
The issue was that I was adding options to &ls_exp_gpio_f, while there is an extra pinconf { ... } level.