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<bamse> z3ntu: odd, not sure why i picked the other two but not that one, thanks for letting me know
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<aka_[m]> konradybcio: morning
<konradybcio> aka_ o/
<aka_[m]> have you scrolled up a little?
<konradybcio> yes
<aka_[m]> So reg for iommu not required
<konradybcio> ranges denotes the (index,) start and size of the child nodes'
<konradybcio> address space
<konradybcio> I asked for reg because the iommu device surely has some registers associated with it
<aka_[m]> when you define reg it overrides register
<aka_[m]> its only one use of it
<aka_[m]> so if i define reg to be address space of childs i risk writing random reg
<konradybcio> reg specifies the register space of the device associated with the node
<konradybcio> ranges is purely for chidlren
<konradybcio> so, the effective child address is (child_base + parent-ranges-base)
<konradybcio> aaand i managed to use snake case and kebab case in one sentence lmao
<aka_[m]> qcom_iommu->local_base = devm_ioremap_resource(dev, res);
<konradybcio> okay, does devm_ioremap_resource return the address specified in ranges?
<aka_[m]> you are developer, not me
<konradybcio> you can add a quick pr_err :P
<aka_[m]> my idea is reg is only used for obtaining local_base
<aka_[m]> which override this register inside SS_LOCAL
<aka_[m]> if i wanted to provide reg i would need to make reg like @1ee0000
<aka_[m]> but still no idea whats a result of rewriting that register
<konradybcio> giving it a quick grep on 3.10, i see that it gets "smmu_local_base" from dts
<aka_[m]> yea
<konradybcio> and then 8916 39 09 set it to 0x1ef0000
<aka_[m]> but thats in smmu-v2 dts
<aka_[m]> later on 8976 branch no register there
<aka_[m]> in regs
<konradybcio> oh you posted something about this , let me read up
<aka_[m]> SMMU_INTR_SEL_NSHYP ADDRESS 0x1000 RW
<aka_[m]> SMMU_INTR_SEL_NSHYP RESET_VALUE 0x00000000
<aka_[m]> INT_APP_CXT_EN BIT[31:0]
<aka_[m]> wrong reg
<aka_[m]> SMMU_INTR_SEL_NS ADDRESS 0x2000 RW
<aka_[m]> SMMU_INTR_SEL_NS RESET_VALUE 0x00000000
<aka_[m]> INT_APP_CXT_EN BIT[31:0]
<aka_[m]> 8916:SMMU_500_REG_WRAPPER+0x000F0000
<aka_[m]> 8976:SMMU_500_REG_WRAPPER+0x000E0000
<aka_[m]> no idea how secure interrupts works
<konradybcio> i think we should simply add a compatible-based quirk here then
<aka_[m]> well it would be best to understand whats even going on here
<aka_[m]> yaml says its rerouting interrupts
<aka_[m]> is it like secure world can take interrupt like it gets gpios?
<konradybcio> the sec/ns split seems to not matter very much here
<aka_[m]> they are 32CB
<konradybcio> this write prooobably just enables all sec irqs
<aka_[m]> "to only 1 line at gic" so every CB just will throw single interrupt?
<aka_[m]> so you get like 3 CBs using same interrupt
<aka_[m]> konradybcio: in ds you posted before it writes to localbase it seems to do __program_iommu_secure
<konradybcio> aka_ yes that's fine.. tlmm also has a single interrupt but then there's registers allowing you to tell which pin changed
<minecrell> aka_[m]: you should be able to ignore SMMU_INTR_SEL_* on any platform != msm8916 since qcom introduced the funny "interrupt aggregation logic" only for 8916 and dropped it again immediately after
<minecrell> but I didn't really get what you are trying to do
<aka_[m]> minecrell: Konrad wants me to provide reg on iommu node and from what I see it's only used to toggle that funny register
<minecrell> I guess if qcom_iommu does support it, the platform does have the register and downstream writes it as well there is no harm to just add it
<minecrell> but I'm 95% sure it will change absolutely nothing
<aka_[m]> It doesn't i guess
<minecrell> that's probably just an historical artifact in the hw
<aka_[m]> Ds have 2 regs in iommu base
<aka_[m]> On 8916
<aka_[m]> Smmu-v2. Dtsi
<aka_[m]> Single reg on 8976/8953
<aka_[m]> Second reg on 8916 specify that smmu_ss_local base containing This rrg
<aka_[m]> Dumb swiftkey
<minecrell> In this case I'd just use whatever works easiest for making bindings and driver happy. If you get warnings when omitting the reg then you might as well specify it and do the redundant write, if there are no warnings you might as well omit it
<aka_[m]> konradybcio: regarding gpu opp table if I haven't said yet freqs bit differ because when porting gcc you have skipped adding gpll3 derived frequencies into gfx3d
<aka_[m]> minecrell: reg is optional
<minecrell> I'm spontaneously not sure how the unit address (iommu@1ef0000) works with just "ranges" but no "reg", so that may be an argument in favor of reg
<minecrell> or do you use the ranges address then?
<konradybcio> yeah i was curious about lack of this warning as well
<aka_[m]> Ain't ranges used my DMA or something?
<konradybcio> ranges are used for child reg calculation
<konradybcio> and for mapping the parent mmio space
<aka_[m]> On 8953 seems it got without reg
<aka_[m]> So guess I'm doing with proper reg if it ain't breaking anything
<aka_[m]> But need testing and latest next probably is bit broken
<aka_[m]> konradybcio: still ain't reg outside of ranges?
<aka_[m]> Like ctxs are before ss_local
<konradybcio> i mean, there may be more than one reg entry
<aka_[m]> <konradybcio> "i mean, there may be more than..." <- can you check rest of those:
<aka_[m]> I haven't tested yaml changes yet
<aka_[m]> sdc yoinked(part of Marijn series),dsi-yamls(picked already by lumag)
<konradybcio> required-opps take a phandle argument
<konradybcio> you can also drop opp-supported-hw since there seems to be no speed bins
<konradybcio> the oppv2 compatible also has a misplaced space
<konradybcio> plus please sort the frequencies from highest to lowest
<konradybcio> plus please put clocks before clock-names and remove the newline bt ween them
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<aka_[m]> konradybcio: haven't you had idea on writing validation tool for props?
<konradybcio> correct
<aka_[m]> When dtc runs on dts I guess it completely changes ordering and all
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<lumag> aka_[m], not really. The order is generally the same. It can change old property if there is an override. I think, that's it
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<JIaxyga[m]> Im a little confused. CX power domain not being added to CCs? Is this hardcoded? I havent noticed it anywhere yet
<JIaxyga[m]> JIaxyga[m]: I mean in device trees
<konradybcio> no, you need to add it by hand
<JIaxyga[m]> konradybcio: Yeah, I see it in x1e80100 and sm6125
<JIaxyga[m]> Ill fix the gcc yaml for sm7150 and take it into account in the rest of the clocks
<JIaxyga[m]> konradybcio: Is it not shared via clocks?
<JIaxyga[m]> I think not, ok
<konradybcio> JIaxyga: bamse promised us that soon you'll be able to hook up multiple power domains
<konradybcio> you'll notice that e.g. the PLLs live on MX
<JIaxyga[m]> konradybcio: So now only one power-domain is supported? According downstream gcc requires cx and cx_ao
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<konradybcio> yes for now only one will be taken into account
<lumag> JIaxyga[m], just use cx for now. Otherwise both will be ignored
<JIaxyga[m]> Thank you very much guys
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<aka_[m]> konradybcio: Since when we got consensus of sorting max->low opp?
<aka_[m]> i see even recent dtses like 6115 still does low to high
<aka_[m]> even opp-v2.yaml does it
<konradybcio> oh..
<konradybcio> we should probably agree on something.. krzk?