06:54 <sgerhold> aka_[m]: I'm quite sure you need both clocks running for (certain?) register accesses to succeed. I guess you can try that, but perhaps the clock is even running by default when the DSP starts. Would need to explicitly "disable" it to be sure

12:15 <aka_[m]> sgerhold: issue is without DIG_CLK enabled in machine driver mi2s fails to start

12:15 <sgerhold> dsp returns an error?

12:15 <aka_[m]> would dumping registers pre and post dig_clk enablement help?

12:15 <aka_[m]> yea

12:15 <aka_[m]> 110

12:16 <aka_[m]> maybe there is some gating?

12:16 <aka_[m]> like top_ctl have its own clock

12:17 <aka_[m]> digital codec kinda does mclk setting

12:17 <aka_[m]> CDC_TOP_CTL RESET_VALUE 0x00000001

12:18 <sgerhold> hm I'm not entirely sure about the startup sequence, perhaps the codec would always already be running at that point

12:19 <aka_[m]> maybe there is something more to it like qdsp also voting for voltages on clock enable

12:21 <aka_[m]> i seen some mentions of lpaif dig codec having to be enabled before afe_port_cmd_device_start is issued

12:21 <aka_[m]> whatever, pm patches could slide i think

12:29 <aka_[m]> sgerhold: i have weird idea

12:30 <aka_[m]> there is a clock on 8953/8976 which seems to not exist on 8916

12:30 <aka_[m]> what is description is wrong

12:30 <aka_[m]> and codec root is 5

12:31 <aka_[m]> guess i should read this register pre/post enablement

13:27 <aka_[m]> Affe Null: out of wonder

13:27 <aka_[m]> have you tested these q6afe patches you made on 8916 while reverting stuff?

13:27 <aka_[m]> i mean making it inline with newer socs

13:28 <aka_[m]> like there is no ahb passed to wcd-digital

13:42 <aka_[m]> great

13:42 <aka_[m]> ADSL dead

13:42 <aka_[m]> wrong chat lol soory

15:25 <JIaxyga[m]> Hey, krzk:. Do you agree with Vladimir's advice?... (full message at <https://matrix.org/_matrix/media/v3/download/matrix.org/kNTXZZqTVrZNELwuuyHtethg>)

15:58 <aka_[m]> sgerhold: uh i took a look at wcd-digital passed clocks and it passes IXFABRIC but also i took a look at other clocks like base AHB ones and it seems on 8916 reset always toggle CLK_OFF bit

15:59 <aka_[m]> not a case on 8976/8953

15:59 <aka_[m]> however enable so bit[0] is also 9

15:59 <aka_[m]> *0

16:01 <aka_[m]> not even mentioning on 8916 there is single register for that and on 8976 there is also SPDMTM one

16:04 <aka_[m]> seems a case on other clocks too

16:04 <aka_[m]> like CODEC_DIGCODEC_CBCR

16:52 <krzk> JIaxyga[m]: just paste the link if you want me to go somewhere...

16:52 <krzk> matrix messages do not work in IRC

16:53 <JIaxyga[m]> https://lore.kernel.org/all/0232aa10-5f40-433b-804a-2fff30e8b143@linaro.org/

16:53 <JIaxyga[m]> Do you agree with Vladimir's advice?

16:59 <krzk> JIaxyga[m]: I don't know, you tell me. Are the clocks valid for sm8450 since they are put in the sm8450 bindings?

17:00 <krzk> Anyway, any include won't work because both headers might go their own way

17:03 <JIaxyga[m]> krzk: No, this clocks is not valid for sm8450. But at the same time we need to have them in this header, as the sm8450 (to support sm8475) driver needs it. So creating sm8475 header file and importing sm8450 is not such a bad idea. In the driver I will replace sm8450.h with sm8475.h

17:03 <JIaxyga[m]> https://github.com/mainlining/linux/commit/94ad697c527862a4dc054a2d1b09cdf78e49a589

17:04 <krzk> JIaxyga[m]: and how will it work when we add one more ID to sm8450?

17:04 <JIaxyga[m]> https://github.com/mainlining/linux/commit/a005ba8fc69f0b252456c5b0e61359926b7f0b40#diff-ac671bb4b182c7a5639210600e54fa8a90ad2badddc91112e3054ce109107952R13

17:05 <krzk> As I said, headers will go their own way. Have their own IDs.

17:05 <JIaxyga[m]> krzk: We define them as NULL in the driver

17:05 <JIaxyga[m]> And then change to:

17:05 <JIaxyga[m]> gcc_sm8450_desc.clks[GCC_GPLL2] = &gcc_gpll2.clkr;

17:05 <JIaxyga[m]> gcc_sm8450_desc.clks[GCC_GPLL3] = &gcc_gpll3.clkr;

17:06 <JIaxyga[m]> if compatible = sm8475

17:06 <krzk> How does it help? I am talking about duplicated define!

17:07 <JIaxyga[m]> What do you suggest then? Completely rewrite the driver for sm8475?

17:12 <krzk> Depends how anyone plans to grow sm8475. It could be one header with sm8475 defines prepended with prefix.

17:19 <JIaxyga[m]> krzk: Just in case, here is the downstream commit:

17:19 <JIaxyga[m]> https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/commit/122cb1175cfba8b7957685f6b7d28e7ee9f56f21

17:19 <JIaxyga[m]> cape = sm8475

17:19 <JIaxyga[m]> waipio = sm8450

17:28 <JIaxyga[m]> krzk: By prefix do you mean GCC_SM8475_GPLL2? Or what?

17:29 <krzk> JIaxyga[m]: yes

17:29 <krzk> rather SM8475_whatever_name

17:29 <JIaxyga[m]> Okay thank you

18:20 <JIaxyga[m]> Then another question for you konradybcio lumag . Where is it better to write sm8475 prefix in the name of structures? At the beginning of the name or at the end or as it is now?

18:20 <JIaxyga[m]> https://github.com/mainlining/linux/blob/c6105586dd74ed2cfa6f6f7fbe357acfe4f5125c/drivers/clk/qcom/videocc-sm8450.c#L49

18:38 <Adrian[m]> https://lore.kernel.org/linux-arm-msm/20240804-sm8350-fixes-v1-0-1149dd8399fe@linaro.org/T/#m5024e9c7de42ea0217f0e94495a2656d1502f7fe lumag just FYI: MASTER_MDP_DISP is used in sm8450.dtsi, your patch breaks it :)