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<iscle>
Hi! I've posted some of the code on GitHub already. It's still not complete, as I'm making sure it's as clean as I can get it for now, but I have a question.
<iscle>
Would it make sense for the file to be named V853, but then coding the pins that are only available for V853 with the "_VARIANT" macro?
<iscle>
My plan would be to have multiple compatible tags on the same driver just like they do it on the v3s driver
<iscle>
However, on v3s the file is named v3s (which is the soc with less ports/pins) and then add the pins from the "superior" v3 with the "_VARIANT" macro.
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<apritzel>
iscle: yes, please support as many chips as possible in one driver. For non-conflicting pins (one chip has it, the other not), I don't think we care much about the variants at all
<apritzel>
often those actually exist in all chips, but are just not connected in every package
<apritzel>
we see this in the H616/H700/T507 for instance: same die, same pinctrl IP, but different packages with different features
<apritzel>
would be good to clarify this for the V85x series as well
<apritzel>
also: do you happen to know how the V83x fits in here? Is that related?
<apritzel>
iscle: also, regarding the pinctrl driver in general: I have reworked the whole scheme, getting rid of this entire table at all, and moving the essential information (the pinmux value) into DT instead
<apritzel>
I will need to rework this again, but plan to use this for the A523. Ideally you would piggy back on this
<apritzel>
iscle: do you have a clock driver? I guess you figured, but that is typically an actual beast ...
<iscle>
apritzel: having the pinctrl definition on the dts instead of the code is definitely a lot better!
<iscle>
and yes, I do have the ccu driver, but the ccu-r driver is still not finished and I want to push both at the same time
<apritzel>
iscle: for a preliminary view this doesn't matter, both are independent. So feel free to push them now
<iscle>
apritzel: is the new pinctrl driver already mainlined? or it's still getting reviewed?
<apritzel>
I sent that a year ago, for RFC, and got some positive feedback from the pinctrl maintainer, with minor comments, but didn't follow up on this yet
<apritzel>
so no, not mainline, but I plan to post this after -rc1
<apritzel>
I actually found the Apple pinctrl driver doing something better (in the way they express this in the DT), so I wanted to use that approach instead
<apritzel>
in any case the pinctrl driver stub for each SoC would stay the same (see that repo also containing that for the V5), it's only the common driver internals that would change, and the DT nodes
<apritzel>
if you post what you have to the CCU driver, I can have a look immediately
<iscle>
Nice! For now I will leave it like this and then once that gets approved I can adapt it
<iscle>
I just pushed the CCU driver to the same repo
<apritzel>
I am knee deep in the A523 clock driver as we speak, so my brain is warmed up for this ;-)
<apritzel>
thanks, I see it
<apritzel>
interesting parallels, PLL_PERIPH0 is basically the same as in the A523, same ridiculous amount of clock outputs ;-)
<apritzel>
first thing I see is that you would to indent the content of the struct definition with one tab
<iscle>
The only thing missing on the ccu driver (as far as I know, at least, this is my first time doing something like this) is that for one of the gates you need to write a "key" to a register, and only then the gate gets unlocked and you're able to enable it.
<iscle>
It's register 0x0D04, that's the only thing I could not add to the driver
<apritzel>
yeah, typical Allwinner speciality, but I saw a patch of yours adding this to the driver already?
<iscle>
The patch was for the reset bits of the same register, but i'm not sure how to do it for the gate
<apritzel>
this would need to be discussed on the list anyway, I guess
<apritzel>
and I see this key field mentioned in the sun20i-d1 driver already, but we cheekily ignored this whole clock ...
<apritzel>
maybe we can do the same? What clock
<apritzel>
... is that?
<apritzel>
watchdog?
<iscle>
in d1 driver the ignored gate is for the main cpu clock, which is by default enabled (0x1), but i this ocasion it's for the riscv (second cpu) that is by default disabled (0x0)
<apritzel>
I see
<apritzel>
yeah, ignore this for now, we can tackle this detail later
<apritzel>
depending on how we use the RISC-V core, the kernel might not care anyway
<iscle>
apritzel: what do you mean with "first thing I see is that you would to indent the content of the struct definition with one tab"? which one? i'm looking at other drivers and i see the indentation is the same
<apritzel>
line 33, lines 42-50, 56-66, and so on
<apritzel>
they all start at the beginning of the line, and they shouldn't
<apritzel>
simply speaking you have only the "static" and "#define" at the beginning of the line
<apritzel>
not sure which drivers you are looking at?
<iscle>
hmm they do have 1 tab indent, are you sure it's not your code editor? or github if you're looking at it online haha
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<apritzel>
ah, indeed, sorry, it's the github diff view
<apritzel>
how stupid is that?
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<iscle>
ever since microsoft bought github, the web ui has been going downhill
<apritzel>
iscle: so the driver looks roughly sane, but of course I didn't check this thoroughly yet
<apritzel>
checkpatch only complains about lines 166 and 167 having spaces instead of tabs at the beginning
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<apritzel>
but consider this one ready for a post
<iscle>
the spaces are because of vscode defaulting to 4 spaces for indentation... i'll get it fixed
<apritzel>
but vscode should know about the kernel coding style?
<iscle>
I haven't configured it tbh, I do all formatting by hand normally haha
<apritzel>
I thought that was the whole point of using vscode? That it helps you out in all possible ways?
<iscle>
I only use it because it has a handy search tab that is fast, for the syntax highlighting and for the project browser. Everything else I don't use...
<iscle>
If you have other tool suggestions, I'm always open to try new things
<iscle>
But, I have to say, my favourite IDEs are JetBrains's
<apritzel>
you use the editor you know best and that you feel most comfortable (and fast) with
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<apritzel>
and since you are not the only one using vscode for kernel development, I am pretty sure it knows how to observe kernel coding style ...
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<iscle>
I've pushed all changes except ccu-r and dts. Commit history will have to be redone, of course. I think I fixed all formatting issues in all the files that have been pushed.
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<dsimic>
mmm, the A523 looks yummy :)
<apritzel>
dsimic: the T527 is much tastier ;-)
<apritzel>
(same die, though, the T527 just connects more peripherals to pins)
<dsimic>
oh, that's nice
<apritzel>
mainline booted to the prompt on Thursday, albeit with a minimal (fake) DT to completely ignore the CCU
<dsimic>
what A523- or T527-based boards are avaliable and you'd recommend?
<dsimic>
nice job!
<apritzel>
A523 is only in tablets (Teclast P85T), I got one last year, but it's hard to work on, not very hacker friendly (secure boot and no serial and such)
<apritzel>
the T527 is on the Avaota A1, a nice development board, on Aliexpress for ~ 40 USD
<apritzel>
also on some more expensive (more professional) development boards
<apritzel>
then there is the H728, which is probably again the same die in a different package, available in TV boxes (on Aliexpress)
<apritzel>
will probably get one of those as soon as the basics are working
<apritzel>
firmware is somewhat hackish at the moment, to work around the missing OpenSource DRAM init, but I was able to run mainline U-Boot, and USB (2.0) and MMC worked
<dsimic>
the Avaota A1 looks great indeed
<dsimic>
thanks for the info!
<dsimic>
sssh... there's file named "'SCH_Avaota A1_PINE64_2024-07-02.pdf'"
<dsimic>
_maybe_ there will be another board :)
<dsimic>
'This VERSION is modify LOGO for PINE64.txt' :)
<apritzel>
yeah, there is some collaboration going on, I think Pine64 manufacturing boards, after all it's OSHW
<apritzel>
I got mine from Pine64, actually, through gamiee
<dsimic>
looking forward to the Pine64 version
<apritzel>
anyone familiar with PCIe internals? Since the pins are shared with USB3.0, I wonder if one can hack those signals to some PCIe/M.2 slot. The PCIe refclk signals are grounded on the board, can one work around this?
<dsimic>
maybe an external clock generator could be used
<apritzel>
I guess they need to match exactly, in frequency and phase, which means some other 100 MHz source wouldn't do?
<dsimic>
I'm not sure
<apritzel>
the manual says the clock can be injected from an external generator, through those two pins on the SoC, but again those pins are not accessible ...
<dsimic>
then it looks like impossible
<apritzel>
yeah, and they are shorted together, and straight to GND, so one cannot even knock off a resistor or so :-(
<dsimic>
that's a bit unfortunate :/
<apritzel>
ah yeah, and the 1.8V and 0.9V PCIe supply inputs are also grounded, so that wouldn't work anyway
<apritzel>
I guess it's Open Source, so one can spin their own version ;-)
<dsimic>
I wonder how much one such board end up consting :)
<dsimic>
oops... s/consting/costing/
<apritzel>
to produce, you mean?
<dsimic>
gah... I wonder how much one such board would end up costing :) *
<dsimic>
sorry for the typos
<dsimic>
yeah
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