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<maz>
marcan: now have a skeletal PMU driver. has anyone documented the PMU events, apart from the two fixed counters? I've sort of worked out that event 2 is most likely cycles too, but that's about it.
<marcan>
maz: I don't think anyone has
<marcan>
currently fighting AICv2
<maz>
huh...
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<maz>
as it turns out, SYS_APL_PMSR_EL1 cannot be written to (it UNDEFs).
<maz>
I guess clearing the overflow is done by clearing the interrupt...
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<marcan>
maz: so it looks like AIC IPIs are gone in aic2, do you have any particular preference for implementing fast (sysreg/fiq) IPIs?
<marcan>
(I also can't for the life of me figure out IRQ affinity... it seems it just tries cores in order with a delay, with a global bit to select whether to start with pcores or ecores...)
<marcan>
(there is a 4-bit per-irq config field that could be a routing config, but only 0 works for me)
<maz>
marcan: eh, if we need them, we implement them!
<maz>
are they still presented as FIQ on the receiving end?
<marcan>
maz: yes, they work the same way as on M1, that hasn't changed
<marcan>
AIC just lost its legacy IPIs
<marcan>
maz: any preference as to how to organize it? stick it in the AIC driver, or try to split it into a separate irqchip?
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<maz>
marcan: if we can keep a single driver, I'm all for it. if you feel that the programming model has diverged too much, we write a new one. no big deal.
<marcan>
the vIPI stuff can be shared
<marcan>
AIC itself is similar enough; I just need to indirect register offsets since they all moved, and have some conditionals in init paths
<maz>
I though as much. I guess the affinity management would be different, but we can also probably migrate M1 over to sysreg-based IPIs, right?
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<marcan>
yeah, I'd do that (and just trigger on the t8103 compatible, so the legacy IPIs can stay for retro chips)
<maz>
sounds like a plan. do people actually work on enabling Linux on pre-M1?
<sven>
iirc there were a few people who were interested but i haven't seen any code yet
<marcan>
I'm not going to spend much time on it, but I also won't gratuitously break code that might work there
<marcan>
maz: so this looks like it supports multi-chip systems (at least it has two interrupt blocks and I can figure out how the second one works even though it's idle)
<marcan>
however, now we have another dimension for the phandle args
<marcan>
for M1 we used <0 nr flags> for IRQs and <1 nr flags> for FIQs
<marcan>
we could encode the die||irq into nr, or we could start accepting a 4-cell form
<marcan>
thoughts?
<marcan>
(cc robher)
<maz>
marcan: that's odd. it means that an interrupt is strictly routed to a particular die? I would have expected SW to be able to route the interrupt to any CPUs...
<maz>
or is that still possible, and the die is just an extra routing hop?
<marcan>
the irq *source*
<marcan>
presumably they have some kind of arrangement where AIC on one die forwards to AIC on the other or so
<marcan>
so that you can handle all the IRQs from one AIC, but you get one sub-block per die in it
<marcan>
so IRQs are now identified as die, hwidx
<maz>
OK, so that's not that different from the multi-chip GIC implementations, except that it is transparent to SW.
<maz>
(transparent on the GIC, not on AIC)
* robher
has little opinion on how you interpret the cells. It's irq provider specific.
<maz>
marcan: my experience with GICv1/2 where we shoved the PPI affinity in one of the cells makes me want to use an extra cell.
<marcan>
sgtm, I'll try that
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<maz>
sven: do you have a dump of the max/pro id registers somewhere?
<sven>
i don't have a max/pro
<maz>
ah!
<sven>
i was close to ordering one but somehow managed to stop myself and wait for the rumored mini with a dual chip M!
<sven>
*M1
<maz>
yeah, I don't really uses laptops for anything other than a glorified remote desktop. so +1 for a boosted mini or something that can live in the rack...
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