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08:38
<
j_ey >
kettenis: am I misunderstanding something.. FIFO size is 16, bu TX/RX AVAIL is 255?
09:18
<
kettenis >
that does indeed appear to be the case
09:18
<
kettenis >
although I didn't investigate that bit thoroughly
09:18
<
j_ey >
I was thinking AVAIL was how much was actually in the FIFO
09:20
<
kettenis >
yes, it is effectively a fifo fill level
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10:06
<
marcan >
oh, this is weird. doing the msr(s3_4_c15_c10_4, 0) thing at init actually breaks the hypervisor.
10:07
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10:08
<
marcan >
wonder if it breaks when IRQs get delivered to CPUs that the guest hasn't started yet? but the IRQ controller is supposed to time out and send them to all CPUs anyway...
10:20
<
marcan >
oh huh, it's not broadcasting now, hm
10:23
<
kettenis >
still fighting with the new AIC?
10:25
<
marcan >
kinda, I was going to do pcie, then realized the change broke the HV
10:27
<
j_ey >
kettenis: first few byte of the initial corrupted packet: a0 80 00, (and the corruption is due to crc16 failing)
10:29
<
kettenis >
is that the packet crc failing? or the message crc?
10:30
<
j_ey >
kettenis: oh hm, not sure which actually
10:31
<
kettenis >
the packet I'm actually interested is, is one that starts with 0x20
10:31
<
kettenis >
so a "read" packet
10:32
<
j_ey >
kettenis: message
10:33
<
marcan >
ah, I think the 8 "delays" registers are actually config of some sort, let's see
10:41
<
kettenis >
j_ey: so I think that is a valid packet, but one that doesn't actually contains a "message"
10:51
<
marcan >
ah lol, I figured it out
10:51
<
marcan >
it happens because the CPUs are in a wfi loop
10:52
<
marcan >
and I guess that counts as something like "hey, I'm good to take an IRQ" and somehow it never times out
10:52
<
marcan >
maybe it keeps retrying the same CPU?
10:54
<
marcan >
yeah, works fine if I switch to wfe mode, welp
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14:45
<
marcan >
ok, so this at least gets pcie not to crash on m1pro, but the links don't come up yet
14:45
<
marcan >
# [cpu1][0xfffffe0012d5bb80] MMIO: W.4 0x580000004 (apcie[1], offset 0x04) = 0x0
14:45
<
marcan >
p.write32(0x580000000 + 0x4, 0x0)
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15:19
<
marcan >
ok, pcie fuse bits changed for one
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<
marcan >
... and the pcie fuse application code in m1n1 is completely broken :D
15:47
<
marcan >
now I'm surprised this worked in M1...
15:50
<
maz >
marcan: PCIe got merged over the weekend, it's time to break it!
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<
marcan >
well, not getting anywhere so far :p
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