ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<j_ey> kettenis: am I misunderstanding something.. FIFO size is 16, bu TX/RX AVAIL is 255?
<kettenis> that does indeed appear to be the case
<kettenis> although I didn't investigate that bit thoroughly
<j_ey> I was thinking AVAIL was how much was actually in the FIFO
<kettenis> yes, it is effectively a fifo fill level
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<marcan> oh, this is weird. doing the msr(s3_4_c15_c10_4, 0) thing at init actually breaks the hypervisor.
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<marcan> wonder if it breaks when IRQs get delivered to CPUs that the guest hasn't started yet? but the IRQ controller is supposed to time out and send them to all CPUs anyway...
<marcan> oh huh, it's not broadcasting now, hm
<kettenis> still fighting with the new AIC?
<marcan> kinda, I was going to do pcie, then realized the change broke the HV
<j_ey> kettenis: first few byte of the initial corrupted packet: a0 80 00, (and the corruption is due to crc16 failing)
<kettenis> is that the packet crc failing? or the message crc?
<j_ey> kettenis: oh hm, not sure which actually
<kettenis> the packet I'm actually interested is, is one that starts with 0x20
<kettenis> so a "read" packet
* j_ey rebuilding
<j_ey> kettenis: message
<marcan> ah, I think the 8 "delays" registers are actually config of some sort, let's see
<kettenis> j_ey: so I think that is a valid packet, but one that doesn't actually contains a "message"
<marcan> ah lol, I figured it out
<marcan> it happens because the CPUs are in a wfi loop
<marcan> and I guess that counts as something like "hey, I'm good to take an IRQ" and somehow it never times out
<marcan> maybe it keeps retrying the same CPU?
<marcan> yeah, works fine if I switch to wfe mode, welp
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<marcan> ok, so this at least gets pcie not to crash on m1pro, but the links don't come up yet
<marcan> # [cpu1][0xfffffe0012d5bb80] MMIO: W.4 0x580000004 (apcie[1], offset 0x04) = 0x0
<marcan> p.write32(0x580000000 + 0x4, 0x0)
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<marcan> ok, pcie fuse bits changed for one
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<marcan> ... and the pcie fuse application code in m1n1 is completely broken :D
<marcan> now I'm surprised this worked in M1...
<maz> marcan: PCIe got merged over the weekend, it's time to break it!
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<marcan> well, not getting anywhere so far :p
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