ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<marcan> sigh...
<marcan> I guess I need to review that one :p
<dhewg> lol :P
<sven> maybe point him to alyssa's version which is already cleaned up a bit
<dhewg> mac via cmdline is prolly not acceptable anyway
<dhewg> via module arg I mean
<sven> yeah, alyssa’s versions takes it from the device tree
<j_ey> why is that v3, I see no other versions
<sven> Probably the first time they submitted something to the ML. Takes a while to get used to it and eventually accept that the only sane way is git send-mail
<j_ey> oh.. 3 patches in the series, v3, maybe some confusion there
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<marcan> replied
<marcan> also threw some shade at stan :p
<j_ey> poor stan
<sven> :/
<j_ey> marcan: 286 firmware files... is that for all the different macs?
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<j_ey> so much less gunk in alyssas series for brcfmac
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<dhewg> where's that series?
<dhewg> ah thx, yet another alias, can't have enough of those!
<chadmed> wow that brcmfmac patch really isnt very good
<j_ey> marcan: are you planning on pushing your linux branch from the stream?
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<marcan> j_ey: yes, once I commit it properly
<marcan> 286 files is for all possible board/antenna/vendor/etc combinations
<marcan> but a lot are copies/symlinks
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<j_ey> but does it contain all the old intel mac firmware too?
<chadmed> ohhh its directly ripped from corellium's fork that explains it lmao
<maz> marcan: do max/pro have a similar cluster layout as m1, where MPIDR_EL1.Aff2 indicates whether the CPU is E or P?
<maz> I end-up having do know that for the PMU...
<maz> (stupid big-little strikes again)
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<marcan> maz: yes
<marcan> MPIDRs are 00000[01] 000001 01010[0-3] 0102[0-3]
<marcan> er, minus the second one
<marcan> maz: fwiw here's the initial bringup from last night: https://github.com/AsahiLinux/linux/commit/e4432729d38916392479252260c8434870a50922
<marcan> (plus the next commit in t6000/bringup-work for the DART fix)
<sven> oh... ouch. so it just took the paddr straight from the PTE when walking the table
<sven> er. wait. the other way around. it put the paddr straight to the PTE when installing a table
<sven> and then when walking the table later everything exploded
<maz> marcan: looking good! if you want to split the fast IPI from the t6k bring up, that could trickle into upstream quickly (5.17).
<marcan> yeah, I'll try to break it up into the compatible/fastipi handling first, and then add t6k / groups
<marcan> sven: yeah
<marcan> it's clearly a bug
<marcan> how did that ever work with 52-bit addrs?
<sven> yeah, probably makes sense to send that separately from the t6000 dart stuff
<marcan> yeah
<sven> i think "iommu/io-pgtable:" is the iommu style commit prefix and make sure to cc robin murphy if get_maintainers.pl doesn't include him automatically
<marcan> maz: I was wondering about the division in the mask/unmask functions; alternatively I could make hwirq sparse and use bitfields, but at that point I really need to move to irq_domain_create_tree
<marcan> however, with ~3000 hwirqs at this point even without holes (but with 2 groups), maybe that makes sense already?
<marcan> sven: thanks, and yeah, the commits are BS right now :-)
<marcan> whole thing needs to be redone and reworded
<marcan> (also comments are wrong etc)
<sven> yeah, just making sure you don't need a v2 just because the commit prefix is slightly off :-)
<j_ey> sven: now you're the eager one :P
<sven> j_ey: true :D
<maz> marcan: +1 for a tree. it would even make sense today, where we only use a handful of interrupts, and yet allocate a fixed-size domain.
<marcan> tree it is then, and then I'll just split the hwirq numbers into 16/16 bits and avoid the division
<j_ey> marcan: how many interrupts did AICv1 have?
<marcan> up to 1024 I think? 700-odd in practice IIRC
<j_ey> ok, so quite a big jump
<marcan> well, AICv2 has up to 4096 per block
<marcan> but the current implementation has 1806 implemented, times 2 blocks
<marcan> only one of which is in use right now
<marcan> I strongly suspect the second block is where the second die's IRQs will show up on the rumored 2-die systems
<marcan> though currently macOS ignores it completely (doesn't even set the masks)
<marcan> it does work though, I can sw_gen IRQs in the second block and unmask them and they get delivered
<marcan> so I implemented support for it, maybe I'll get lucky and the 2-die systems will need no AIC patches ;)
<sven> :>
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<kettenis> one can hope...
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<kettenis> marcan: any progress on the pmgr bindings?
<marcan> kettenis: was kinda hoping for more review comments, since other than the spurious |s in the DT bindings I think everything else is kosher?
<marcan> Krzysztof didn't comment on the v2 of the serial runtime-PM patch yet
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<kettenis> the discussion about the compatibles confused me a bit, but do I understand correctly that you don't plan to remove the apple,pmgr one from the parent node?
<kettenis> if the number of child nodes gets large, I may want to use that in OpenBSD to avoid cluttering dmesg
<kettenis> attach a single driver to the parent node instead of separate drivers to the child nodes
<kettenis> (we print a line for every driver that attaches)
<marcan> yeah, apple,pmgr can stay
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<maz> hopefully, this will give someone an incentive to work out the semantics of the counters...
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<kov> sven, does that mean 2 M1 chips for the next mini? so 16 cpu and gpu cores?
<sven> Your guess is as good as mine
<kov> I'm placing my bet on them doing an A15-based M2 only for the mini to keep that higher end for the iMac Pro
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<jannau> maz: xnu source code has/had counter defines in osfmk/arm64/kpc.c http://www.jannau.net/kpc.c
<jannau> instructions are probably 'CPMU_INST_A64 0x7a'
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<jannau> just the defines assuming m1 is not the early cpu PMU: https://paste.debian.net/1218089/
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<maz> jannau: 7a never seems to count anything here.
<maz> jannau: on the other hand, 78 (which is supposed to be AArch32) does count something.
<j_ey> jannau: didnt you copy the wrong side of the define?
<maz> just not the same thing as instructions
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<maz> j_ey: the other side isn't any better.
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<marcan> kov: 2 M1 Max chips
<marcan> M1 cannot do multi-die
<marcan> a bunch of the changes in M1 Pro/Max are for this
<marcan> 2x M1 makes no sense, that's already a chip called the M1 Pro.
<krbtgt> i'll note the intel mac mini still exists and would prob call for M1 Pro/Max in its replacement
<krbtgt> the plain mini has tons of dead air to fill
<TheLink> isn't there supposed to come a redesigned mini (+ max/pro)?
<krbtgt> thatt's rumoured for prob a spring even
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