ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<kode54> what even is the point of disabling linear-sq?
<kode54> faster random access?
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<sven> I guess it’s for the t2 where the whole nvmmu doesn’t make much sense
<sven> And there nvme is attached over pcie so you “just” need a few quirks to the normal driver to make it work in that mode
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<marcan> maz: so in apple-pcie, we don't actually do anything with the max link speed
<marcan> also there's some extra stuff that has to happen with the designware registers to make it train at the right speed on the first go (ASPM ends up making it retrain anyway, but that's after linux complains about a speed bottleneck)
<marcan> remind me again why we aren't reusing any code from drivers/pci/controller/dwc? It's the same registers for the parts that are shared...
<marcan> (that codebase does the speed dance properly that apple-pcie doesn't)
<kettenis> the existing dwc code has the 1 contoller 1 port assumption throughly built in
<kettenis> s/throughly/thoroughly/
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<marcan> I kind of hate that. It's poking config space registers, but since this is before the PCI bus gets initialized, we can't use the usual accessors...
<marcan> Also, the pmgr stuff in t6000/bringup-work is what I'm going to send as v3, modulo I need to do a final check to make sure I didn't do anything silly :)
<marcan> main changes are I enable auto-PM now (unconditionally, seems to be fine) and also force on "always-on" things that aren't, but complain. There's also a bit of cleanup/fixes, and also the t6000 compatible in the bindings.
<marcan> also I'm outright adding the entire t8103 pmgr tree instead of just a subset
<kettenis> marcan: some of the link speed related setup is actually done by the tunables applied by m1n1
<marcan> not this one though
<marcan> you get this: [ 0.266469] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link)
<marcan> because without PORT_LOGIC_SPEED_CHANGE preset (can be done before initial link training), it just comes up at Gen1
<marcan> the max speed thing is tangential, it defaults to Gen4 but still comes up at Gen1 without that bit
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<kettenis> marcan: since you rebased the PMGR stuff on top of a tree that has more stuff than what has been submitted upstream so far, the bits that actually add the nodes to the device tree won't apply
<kettenis> not really a problem since you're probably going to end up applying those yourself
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<kettenis> otherwise it looks good
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<marcan> kettenis: yeah, I know, I'll rebase that anyway; I'm just using this branch as my kitchen sink to exercise the patches
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<jannau> marcan: does the branch work for you on the mac mini? pmgr seems to cause here a SError in apple_dart_hw_reset of the PCIe dart
<marcan> it does; that sounds like a power domain not set properly?
<marcan> actually I'm testing in the hypervisor, haven't tested bare metal
<jannau> testing baremetal here
<jannau> seems to be the same problem in the hv
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<jannau> can you test without a display?
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<marcan> still no SError without a display
<marcan> can you paste it somewhere?
<marcan> dmesg too
<marcan> also did you compile in the PMGR driver? :)
<marcan> unrelated (probably) but that dispdfr_be thing is interesting
<marcan> that's saying there's a missing parent relationship or so
<marcan> I don't get that though :/
<marcan> oh wait, I do lol
<marcan> heh
<marcan> hold on, what
<marcan> [cpu1][0xffffc0001049cf50] PMGR: W.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x300 -> 0xf
<marcan> [cpu1][0xffffc0001049d034] PMGR: R.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x3ff
<marcan> [cpu1][0xffffc0001049cf50] PMGR: W.4 0x23b7003a8 (DISPDFR_FE.pstate + 0x00) = 0x3ff -> 0x10000300
<marcan> .... that doesn't make any sense
<marcan> why is it shutting it down again
<marcan> ... because I'm an idiot
<marcan> jannau: pushed a fixup, though I don't know if it'll help your pcie problem
<marcan> jannau: can you run it with `-m hv/trace_pmgr.py` (which I just pushed) and paste the HV side log including the SError dump?
<jannau> sure. it does not fix the dart issue
<kettenis> does your DT have the necessary power-domain properties on the dart nodes?
<jannau> yes, the dts in the branch has the power-domain properties
<marcan> jannau: read32(0x23b7003e8)
<jannau> 0x1f0020ff
<marcan> read32(0x23b7001b8)
<jannau> 0x1f0000ff
<j_ey> (m1n1 supports irc proxy now, cool!)
<marcan> I assume read32(0x682008060) SErrors?
<jannau> yes
<marcan> ^\ out of the hypervisor (without rebooting) and run tools/dump_pmgr.py
<marcan> (this is a bit of a limbo state inside the HV but not on the host side, but it should work)
<marcan> only thing I can think of is we're using different iBoot versions and there's some difference
<jannau> should be iboot 12.0.1 on my side
<jannau> another potential difference is that iboot doesn't detect my display but we should be good if you tested without display connected. also unclear how it would be related
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<marcan> I did test without display
<marcan> I need to get some sleep, but I'll try updating to 12.0.1 tomorrow
<marcan> not seeing anything obvious in the pmgr dump :/
<marcan> you could try removing pmgr nodes and seeing if it works at some point
<marcan> though I think you aren't even at the point where it starts turning things off
<marcan> so I really don'tknow
<j_ey> marcan: I thought you woke up early.. lol
<marcan> yeah... this cold has also screwed up my sleep schedule
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<jannau> it boots with all not always on pmgr nodes removed and the power domains commented out
<jannau> it looks like it's the gpio power domain
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<jannau> seems like a dependency problem. with the power-domain pinctrl_ap doesn't get probed
<jannau> the pinctrl devices are probed before the pmgr ones