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<sven>
looks like joro just merged t6k dart :)
<marcan>
\o/
<_jannau_>
\o/
<marcan>
I should submit t8110 soon then, hopefully that one won't ruffle any feathers since it's just driver stuff
<_jannau_>
there should be minimal io-pgtable-dart changes too but I suppose those will be less problematic as well as we are more ore less solely responsible for it
<_jannau_>
marcan: I would expect a change which prevents using more than 1 ttbr
<_jannau_>
no functional changes but a little bit of sanity checking which should never been hit
<marcan>
_jannau_: I think setting ias properly should take care of that
<marcan>
_jannau_: did we even ever support multiple TTBRs? Right now we set ias to 32, which will always result in one TTBR
<marcan>
one TTBR is enough for ias <= 36
<sven>
for the 4k iphone darts, i think someone is using that downstream
<marcan>
ohhh so *that* is why there were 4 TTBRs
<_jannau_>
I kept it only for 4k support
<marcan>
that gives you 32 bits of ias
<marcan>
okay
<_jannau_>
dcp on m2 will need ias == 36
<marcan>
yeah, we should fix that
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<landscape15[m]>
Do you have future plans to implement a vGIC distributor struct in m1n1. I think there is a dev working on that
<j`ey>
amarioguy was/is
<landscape15[m]>
Yes he’s him
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<j`ey>
but I dont think there's a need for linux?
<landscape15[m]>
No it is not needed. But it’s still required for porting Windows
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<chadmed[m]>
is that something that is even possible without microsoft's direct blessing
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<chadmed[m]>
unless youre talking about porting the NT 5.3 source branch, but iirc no one managed to ever get that building fully
<marcan>
it is, under a hypervisor with vGIC support
<marcan>
basically virtualize enough for the core kernel to boot (mostly vGIC) and write drivers for the rest
<marcan>
bare metal is not without microsoft support, no
<landscape15[m]>
From what I know Windows need some sort of GIC/IOMMU initialization (what about Linux?)
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<marcan>
it's not initialization, it has to be fully virtualized
<marcan>
windows cannot run on M1 bare metal because the core kernel does not support AIC/DART
<marcan>
that requires microsoft cooperation to implement
<sven>
simulating DART via SMMU is going to be... "fun".
<marcan>
yeah, heh
<sven>
for some values of fun
<landscape15[m]>
thank you I didn’t know that.
<landscape15[m]>
though porting an old version of NT kernel would be some fun
<marcan>
I don't think porting an old version of NT that didn't even have 64-bit support to ARM64 is going to be exactly "fun"
<chadmed[m]>
there is absolutely nothing fun at all about that source tree, it's very very very cursed
<_jannau_>
does windows for arm supports 16k pages? if not hanling the iommu will get more fun
<j`ey>
Im assuming, like linux, it's hardcoded to (4k) at build time
<marcan>
looks like it's 4K only, so yeah
<sven>
even more fun! :P
<sven>
i'm still half surprised it was possible to make the linux iommu system work with 16k-iommu/4k-cpu pages. and that was with access to the full source code
<marcan>
I should look into how they pulled off mixed page size processes in xnu, I'm still surprised that actually works
<marcan>
I know they just have separate page ops for the actual VM management, but I mean the interaction with the rest of the kernel
<sven>
yeah, that's also quite an impressive hack they pulled off
<sven>
oh... i also noticed that robin's iommu_set_bus cleanup has been merged.
<sven>
one less excuse to continue ignoring that 4k patch :D
<sven>
ah, nvm, the next stage of that is still missing
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<marcan>
sven: I gave the xnu thing a skim and I don't see any magic, other than that they made the entire VM subsystem for ARM support mixed page sizes.
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<marcan>
maybe the rest of the kernel just doesn't assume PAGE_SIZE is real that much?
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<marcan>
they do have this though, but this is system-global
<marcan>
#define PAGE_SHIFT vm_page_shift
<marcan>
#define PAGE_SIZE vm_page_size
<marcan>
#define PAGE_MASK vm_page_mask
<marcan>
so I guess that's what Linux would have to do to make page size selectable *at boot time*
<j`ey>
seems like there is also vm_kernel_page_size
<marcan>
I think lina was wondering how they stopped the CPU tlbi from shooting down random userspace TLBs when shooting down GPU TLBs?
<marcan>
sounds like they just... carve out the entire GPU AS from userspace. lovely.
<marcan>
that one is going to be fun to implement in Linux...
<maz>
don't they have the notion of ASID in the GPU?
<marcan>
yes, they do, it's just 0-63. you *could* carve out the CPU side ASIDs instead.
<maz>
we already have that.
<marcan>
oh?
<maz>
yeah, for SVA.
<maz>
(sharing the userspace PTs with the SMMU)
<marcan>
huh
<marcan>
is that configurable?
<maz>
you just mark some ASIDs as resserved, IIRC.
<marcan>
interesting
<maz>
that'd be a marginally different usage of the feature, but that should hopefully help.
<marcan>
do you have a link/keyword to find this?
* maz
digs
<maz>
grep for pinned_asid_map
<maz>
currently, this is only used to ensure that the ASID allocated to a process doesn't change, so that SMMU and MMU are kept in sync.
<maz>
but it wouldn't take much to turn this into a reservation mechanism.
<maz>
only problem is that M1 is pretty poor on the ASID front.
<marcan>
yeah, 8 bits was it?
<marcan>
so the GPU would eat 1/4 of that
<marcan>
(assuming they all get reserved upfront - this *could* be dynamic I think?)
<maz>
can it do with less?
<marcan>
I think if you limit the number of simultaneously mapped GPU VMs?
<maz>
I'm happy to limit that to 1 (or less... ;-)
<marcan>
I'm not sure GPU performance would appreciate that :p
<maz>
can't please everyone! :D
<marcan>
something something module parameter?
<maz>
yeah, something like it
<maz>
I think this is an interesting avenue to explore. you need a userspace context to perform the TLBI anyway, and pinning the ASID between the CPU task and the GPU makes some sense.
<maz>
you just need to explain to the arm64 mm subsystem that the IOMMU only has 6 bits of ASIDs...
<marcan>
better ask lina about how the VM works/should work exactly. I'm not sure it's 1:1 to userspace processes.
<maz>
if that's not the case, then we may need something else.
<marcan>
well, it can't be, since the same process is allowed to open /dev/dri/* multiple times and file descriptors can be passed aroudn
<marcan>
*around
<maz>
huh
<marcan>
so yeah, probably just something to have the driver ask mm for an ASID/release it as needed? I'm not sure it's actually 6 bits, it might be more. IIRC it's just macOS did a 1:1 map to context slots.
<marcan>
guess that's easy enough to test with some aliasing and TLB shootdowns
<marcan>
I think you'd basically just want new_context(), but a generic version that doesn't take a mm_struct but rather just the ASID-relevant bits from it.
<maz>
something like that indeed.
<marcan>
and then you also need some kind of hook to flush the GPU TLB when a previously GPU-mapped ASID gets reused by another process...
<marcan>
well, I guess that could technically just be done when a new ASID is assigned?
<maz>
Ideally, we wouldn't have to track GPU-specific ASIDs in the arm64 code at all.
<maz>
just invalidating the ASID on allocation is hopefully enough.
<marcan>
yeah, I think if the GPU side just flushes TLBs any time it gets a new ASID that's different from the previous one for that VM, it should work
<marcan>
well, it'd also have to track if an ASID is transiently reused by another VM
<marcan>
but that can be done
<marcan>
could also defer releases a bit, so that userspace process thrashing doesn't thrash nominally active GPU contexts during short idle windows
<marcan>
maz: > you need a userspace context to perform the TLBI anyway
<marcan>
what do you mean by that exactly, by the way?
<marcan>
(also maybe you should join #asahi-gpu :p)
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<maz>
invalidation by ASID relies on the ASID being present in TTBR. if you want to use a GPU-private ASID, you need to switch that TTBR to have the ASID and an enpty set of PTs.
<maz>
empty*
<maz>
my earlier divagation was based on the hope that userspace and GPU could use the same context, making it easy to perform the invalidation.
<marcan>
huh. really? I somehow doubt the macOS driver does that...
<maz>
me checks again
<maz>
ah, maybe not
<maz>
there is TLBI ASIDE1
<marcan>
yeah, that makes more sense
<maz>
takes the asid as a parameter (in the same field as TTBR)
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<marcan>
maz: and all the other ones also take the ASID in the high bits, right? so it doesn't matter if it's in a TTB, you can specify whatever
<maz>
marcan: yeah, I got confused with TLBI by VA, which uses the ASID present in the TTBR.
<marcan>
does it? VAE1 also takes the ASID
<maz>
damn. I'm losing the plot.
<marcan>
maybe you're thinking of the S2 ones? ISAS2E1 and co? those do use the current *VMID*.
<maz>
yeah, I'm probably badly tainted here...
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<sven>
i'm starting to think that whatever is missing for dcpext happens somewhere outside atcphy and dcpext :/
<sven>
which doesn't make much sense either but I'm running out of ideas and things to copy from the macos trace
<sven>
there's still the hdcp endpoint and that mcdp29xx endpoint but those also don't make much sense
<_jannau_>
mcdp29xx doesn't make any sense except on the macbook pro hdmi connector. hdcp seems unlikely
<sven>
yeah. let me try starting that endpoint just in case though
<sven>
nope, no difference. and macos doesn't seem to call any methods on it anyway
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<_jannau_>
have you checked the darts? does macos replicate the shared mem mappings iboot does for dcp,disp0 and dcp,piodma? iirc for dispext/dcpext only dcp text and heap are premapped. I could image thsoe mappings are done by driverc and not via dcp fw commands
<_jannau_>
otoh dcp would probably crash if an expected mapping doesn't exists
<sven>
Let me take a look at the darts again, but anything unmapped crashes xnu on access
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<jannau>
I think it's possible to break disp0 without crashing dcp. I would image that a modeset could fail under that circumstances
<jannau>
I haven't yet monitored what those initial mappings are used for
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<amarioguy>
Landscape15[m]: still working on that but that's offtopic for here
<amarioguy>
sven: expect v2 of the patch this weekend or next weekend btw as a heads up
<amarioguy>
(the patch == i2c stuff, sorry again for delays stuff started picking up on my end)
<amarioguy>
marcan: while offtopic, did want to at least make the comment that dynamically filling in ACPI tables based on FDT (or worse ADT if i ever get around to making a library for that) is a whole level of cursed/fun :)
<amarioguy>
yes read the chat backlog just now as i literally just got back
<j`ey>
amarioguy: there is code in edk2 for fdt->acpi
<amarioguy>
got a source, as that'd be *very* helpful
<sven>
jannau: good to know, I’ll take a closer look once I hate dcpext a bit less again ;)
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<jannau>
sven: it's rather unlikely as those mappings are in pairs for disp and dcp. i.e. if you miss them you most likely will crash dcp
<sven>
I’m otherwise out of ideas tbh
<sven>
well, except for reversing DCP firmware but I’d like to avoid that
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<jannau>
sven: did you change the return value of ServiceRelay::sr_getClockFrequency? 533333328 for dcp and 0 for dcpext
<sven>
huh, no
<sven>
i didnt notice it was supposed to be different
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<jannau>
I didn't either until now. comparing dcp and dcpext traces
<sven>
hm.. doesn't seem to make a different unfortunately :(
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<jannau>
matches disp0.clk[0] and dispext0.clk[0] values in pmgr's boot clocks
<sven>
hrm, looks like that method isn't even called before setting the mode
<jannau>
other obvious difference I see is that it calls set_digital_out_mode() twice for dcpext with different modes
<sven>
in my trace it's only called once
<jannau>
but that doesn't help either when the first modeset fails
<sven>
yeah. i'll try to clean my code up later this week and push it somewhere.
<sven>
maybe having another pair of eyes on it will help
<sven>
it'll only work on t8103 though
<jannau>
except for the rt_bandwidth_setup_ap data no suspicious differences before the first set_digital_out_mode
<sven>
yeah, that matches was I saw when I compared traces :/
<jannau>
differences looks like either timing or capability related
<sven>
maybe i'm also doing something with these additional epic endpoints wrong
<sven>
but i've been over those a few times now
<sven>
or it's something that happens in PMGR or whatever at boot time. tracking that down is going to be very annoying though
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<jannau>
dcpext get a hotPlug_notify_gated() CB here
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<sven>
yea, that happens after you send a notifyHotPlug message to another epic endpoint
<jannau>
if you connect dcpext after the system has booted there should be less pmgr noise
<sven>
i think it always started dcpext for me
<sven>
even with no cable connected
<sven>
but I can try again tomorrow
<jannau>
you're right, it's started at boot
<sven>
and pmgr spams a lot during boot as well
<sven>
and who knows what else
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<amarioguy>
marcan: given that nested virt is on m2 and presumably future chips nowadays, do you mind if i take on the task of adding nested virt support to m1n1?
<amarioguy>
(like setting up VNCR_EL2 and the like)
<amarioguy>
(well m1n1's hypervisor that is i mean, ik KVM already has this implemented this is more for testing KVM while running under m1n1's hv)
<amarioguy>
idk if this would go against design decisions you wanted to uphold with m1n1 but i figured it's worth asking in either event
<marcan>
isn't nested virt quite a bit more complicated than that? don't you have to deal with page table flattening and all that stuff?
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<amarioguy>
is that how KVM does it?
<marcan>
yes
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<amarioguy>
ah gotcha that makes sense, probably need to do more reading on it (i wasn't sure how complicated it would've been ngl as documentation on NV/NV2 is a bit sparse)
<amarioguy>
probably a low priority feature in either event so i'll put the brakes on that for now
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<j`ey>
amarioguy: well the patches to linux for NV are ~60 patches, and up to v6, so it's not that simple!
<marcan>
+5000 lines of code ish for NV support in KVM
<amarioguy>
so much for that at that point we're bloating m1n1 lol
<amarioguy>
if it's on that scale i mean
<marcan>
yeah, I don't think we want this in m1n1
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<jannau>
oh nice. 'fdt_path_offset(dt, "$alias")' works directly
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<jannau>
lol, missing BTI handling in Apple's Webkit javascript JIT compiler breaks on Linus' M2 Macbook Air wifi portal logins
<j`ey>
sad
<jannau>
Gnome Web in Fedora is basicly rendered useless by this
<jannau>
I wonder if has a switch to disable JIT or javascript globally
<j`ey>
cant force it to open in a browser somehow?