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<chadmed>
adding the equal loudness compensator to the pipewire filter chain helps a decent amount with sound quality at low volumes, as youd expect
<chadmed>
however now we _really_ need pipewire to hide nodes from the rest of userspace :P
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<millenialhacker>
ty
<millenialhacker>
ty ChaosPrincess
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<sven>
jannau: hrm, so I don't have a display that actually requires 4 lanes so both pma_single seem to work for me. would be great if you can figure out the right UNK008/UNK100 setting if you have some time!
<sven>
huh, nevermind. apparently it now negotiates four lanes again
<sven>
so I see [PhyTracer@/arm-io/atc-phy1] MMIO: W.4 ACIOPHY_CROSSBAR = 0x114 (PROTOCOL_SWAPPED=0, PROTOCOL=0xa(DP), DPMODE=0x8) for one orientation
<sven>
and [PhyTracer@/arm-io/atc-phy1] MMIO: W.4 ACIOPHY_CROSSBAR = 0x22014 (PROTOCOL_SWAPPED=0, PROTOCOL=0xa(DP), DPMODE=0x1100) for the other one
<sven>
so I guess even both_pma is only set for one of those two
<jannau>
I think I saw that as well but setting both_pma didn't seem to have an effect with UNK008
<sven>
okay, I think swapped is both_pma = false and UNK008
<sven>
and normal orientation is both_pma = true and UNK100
<sven>
let's see if I can move the pipehandler configuration into the phy power_on callback because apparently doing phy_set_mode after xhci init breaks some intel platform *sigh*
<sven>
er.. *doing it before xhci init
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<sven>
also, i'm blind. b'\x00\x00\x00\x000'
<sven>
see how the last byte there is 0 vs \x00? that's the DP SID Status changed interrupt
<sven>
so that's what we can use for HPD even with USB3+DP hubs
<jannau>
superspeed detection works now but either you or I broke DP hotplug detection. rebased again and with local modifications, so it's probablyy me
<sven>
could also be me, I didn’t test the DP hotplug very well
<sven>
but it worked at least once
<sven>
it won’t work at boot time though since there’s still this race between drm and tipd probe
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<jannau>
it looks like it was the monitor. after power cycling it I see the hotplug. unfortunately it results in "phy-apple-atc b03000000.phy: pipehandler lock not acked, this type-c port is probably dead until the next reboot."
<jannau>
port still works though
<sven>
uh oh
<sven>
that’s new, usually when the pipehandler lock thing happens the port is dead
<jannau>
yes, it was previously when usb3 was broken
<sven>
-#define PIPEHANDLER_MUX_MODE_DUMMY_PHY 0
<sven>
+#define PIPEHANDLER_MUX_MODE_DUMMY_PHY 2
<sven>
and
<sven>
-#define PIPEHANDLER_CLK_DUMMY_PHY 2
<sven>
+#define PIPEHANDLER_CLK_DUMMY_PHY 4
<jannau>
pipehandler lock request seems to eventually succeed
<sven>
maybe fixes that
<sven>
i may have accidentally switched pipehandler to either an invalid state or usb4 mode
<jannau>
yes. that fixes it and DP works in both plug orientations with "both_pma = true and UNK100" / "both_pma = false and UNK008"
<sven>
\o/
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<sven>
doing the pipehandler stuff in power_on also works fine
<sven>
let me verify if my new role switch reset quirk still works without a phy present. Then I’ll just have to rework those apple,dwc3 bindings before trying to upstream it
<sven>
no matter how thunderbolt eventually fits into this mess that role switch thing is good enough to bring dwc3 up/down whenever we need it
<sven>
we can probably also soonish enable usb3 in asahi-dev at least. Just want to fix some minor things, move the pipehandler stuff to pwoer_on and test it a bit more
<sven>
but it seems to be very stable here now
<jannau>
please refetch, pushed a cosmetic fix
<sven>
not at a computer right now anyway ;)
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<jannau>
brightness control seems to work reliably now
<sven>
nice!
<jannau>
embracing no drm atomic commits instead of trying to work around them and pretending that backlight control is a form of color management
<jannau>
assuming that the backlight changes which will integrate brightness control with drm will be ready before dcp
* sven
doesn’t even know what drm atomic commits are
<alyssa>
jannau: I have questions
<sven>
anyway, looks like doing the pipe handler dance inside power_on works just fine as well
<sven>
let me clean up tipd a bit, then ideally get confirmation that usb3 works on all machines out there (especially m2) and then I’ll prepare something for marcan to merge into asahi-dev to get usb3 up :>
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<jannau>
alyssa: which are? color management looked like the best fit for backlight control
<alyssa>
these are the 3 lines I'm trying ot make sense of
<jannau>
ah, the '||' should be '&&'
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<alyssa>
Right, ok
<alyssa>
That makes some sense
<alyssa>
But that still doesn't match the commit message
<jannau>
but yes, !fb->format->has_alpha || new_state->plane->type == DRM_PLANE_TYPE_PRIMARY would make sense as well
<alyssa>
which suggests this is used to distinguish XBGR overlays from ABGR overlays
<alyssa>
"!fb->format->has_alpha || new_state->plane->type == DRM_PLANE_TYPE_PRIMARY" is what I would expect this to read
<jannau>
I don't remember, possible that I simple botched the commit and did not notice since I never tested with with that commit and multiple planes in linux
<alyssa>
sure, I have far more embrassing logic errors on the agx side ... not that anyone reads the code ... ;P
<jannau>
thanks for the review
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<joske>
sven: did I hear needs testing on all devices? :-D
<joske>
I only have a M1 MBA though (I also have a M1max MBP, but from work, not allowed to use for personal stuff)
<sven>
not yet, but soon
<sven>
at least usb3
<joske>
ok, let me know when you want to have something tested
<sven>
I’ll ping you once I’m ready
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<joske>
not always online, but I scan the IRC logs daily
<sven>
sure. I’ll also need to nerd snipe someone into reverse engineering the atc fuses for m2
<joske>
A friend of mine has an M2 MBA, and I tricked him into installing asahi on it :-D
<joske>
next up: tricking him into rolling custom kernels :-D
<sven>
those are annoying because they’re not a table in a kext but a function that’s like 1k lines decompiled in ghidra
<sven>
most of that is debug crap though
<sven>
but still... not much fun to find those fuses
<sven>
other alternative is to run the hv and intercept reads from the fuses and the atcphy regs and play with some patterns to figure out which bits go where
<sven>
also not much fun though
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<sven>
but if anyone wants to give it a go i'll be happy to give some pointers in #asahi-re where to find them
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<joske>
:/
<sven>
that UCSI code is much more complex. guess i'll send a mail to heikki to ask if my code that bypasses all of the typec bus stuff like drivers/platform/chrome/cros_ec_typec.c does is acceptable to him as well
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<sven>
alyssa: don't you want to get back into kernel stuff? I hear USB and type-c would be a good new project!
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<alyssa>
sven: nice try c:
<sven>
:<
<alyssa>
sven: I don't even have M2 hardware
<alyssa>
I just have the M1 Mini lol
<sven>
oh, that's fine. I was more thinking about understanding that typec subsystem a bit better and cleaning up my tipd hacks!
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<joske>
povik: my friend has an M2 MBA (running asahi-dev with speakers enabled). After resume from s2idle, only L channel as known, but I saw this in his dmesg: [ 88.576671] tas2764 3-003b: Unable to sync registers 0x1-0x4. -6
<jannau>
marcan: https://github.com/AsahiLinux/linux/pull/65 has dcp backlight control. needs a devicetree and m1n1 update. a test on Macbook Air (2020) would be good to see if brightness is limited to 400 nits
<jannau>
kernel is a little bit noisy on backlight updates but left it there for initial testing
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