ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nickchan>
a11 acts like as if it has like 1.5 clusters in all sorts of ways
<nickchan>
- first the aic does not support cluster fast ipi
<nickchan>
- secondly the mpidr for cpu4 and cpu5 are 0x10004 and 0x10005 respectively
<nickchan>
- thirdly the performance controller is still like a10 where low states represent ecore and high states represent pcore
<nickchan>
but all cores can be active at the same time
<nickchan>
this means that:
<nickchan>
when the ecore is not at its highest frequency, the pcores can only be at their lowest frequency
<nickchan>
when the pcores are not at their lowest frequency, the ecores can only be at their highest frequency
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<nickchan>
there might be some other stuff too when I am 100% sure I will modify the cpufreq driver to account for this
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<nickchan>
this may be tricky too because this means the cpu across cluster are related_cpus but not completely related
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<nickchan>
probably gonna add a new property to the cluster cpufreq node specifying the highest ecore pstate
<nickchan>
as for cpufreq on t8011 we have not got it to work yet
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<nickchan>
I know the pstates are different from t8010 and the performance controller looks like it is at the same address
<nickchan>
however there are some issues that locks the whole system up
<nickchan>
possibly missing some tunables if some pcore tunables are missing issues would not show up till the cpu frequency is attempted to be adjusted due to the fusion arch
<nickchan>
this also means that a11 *cannot* get apple,cluster-cpufreq compatible
<nickchan>
well, unless I apply the a11 logic whenever the new property in cluster cpufreq is present
<nickchan>
and have a11 continue to get the t8103 compatible
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<nickchan>
there's two other ways that i think a11 can work, one more cursed one less cursed, time to go experiment
<nickchan>
I expect G10P AGX DRM support to be even more cursed but currently I am not ready to go into that rabbit hole yet
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<nicolas17>
nickchan: I thought A10 pcore/ecore was cursed but A11 is worse wtf
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<nickchan>
nicolas17: a10 is cursed on the physicl level but it is mostly abstracted away from software
<nickchan>
a11 is probably similarly cursed at the physical level but can't be abstrated to allow all cores to be active at the same time
<nicolas17>
ah right, you can just pretend A10 has two cores with variable performance and ignore the fact that it switches to a different core at a certain perf threshold
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<nicolas17>
nickchan: I read of an Android SoC that had big/little cores with different capabilities and software could SIGILL when migrated between them x_x
<nickchan>
nicolas17: a10 also has that
<nicolas17>
they aren't equivalent?
<nickchan>
they in fact are not
<nicolas17>
arm32?
<nickchan>
arm32
<nickchan>
only hurricane does arm32
<nicolas17>
anything else though?
<nickchan>
Don't think so
<nicolas17>
the kernel can at least handle that
<nickchan>
I mean it's okay at the page size that a10 supports most aarch32 binaries won't run anyways
<nickchan>
so it's not a big loss
<nickchan>
aarch32 linux binaries
<nicolas17>
this was like a specific ISA extension that one core had and the other didn't, so it started running on the pcore, ran whatever is ARM's version of cpuid, determined the feature was supported, used it successfully, then got migrated to the ecore and crashed
<tpw_rules>
i mean intel did that too
<nickchan>
nicolas17: the kernel should be able to handle that
<nickchan>
people mix and match cpus all the time in arm socs
<nickchan>
and the kernel only expose a safe value
<nickchan>
what the upstream kernel cannot currently handle is something like the arm32 situation on a10
<nicolas17>
well the android vendor's shit kernel didn't, and the userspace app had to figure out what to do about it (after the hell in figuring out what the problem was) :D
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<nickchan>
okay APPLE_DVFS_PLL_STATUS and APPLE_DVFS_PLL_FACTOR seems to be related to getting frequency from hw
<nickchan>
but the comments are not very clear on how exactly to get the frequency
<nickchan>
and the driver does not get frequency from hw
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<nickchan>
okay a11 cpufreq is even more cursed than i thought
<nickchan>
to the point where I am considering *not* use apple_soc_cpufreq
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<nickchan>
i don't have any words for it just see the results
<nickchan>
I guess maybe not since the pro/max chips has more than 1 p/e clusters
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<chadmed>
theres only one e cluster and the p clusters can switch independently
<chadmed>
on the ultra socs the e clusters can also switch independently
<chadmed>
if we wanted to be strict with opp-shared we'd need to dupe the opp tables for each cluster
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<nickchan>
got some figures on a10 cpu voltage gonna add into the device tree for documentation purposes
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<nickchan>
i just realized
<nickchan>
i have no provision of describing the cache in a10
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<nickchan>
in the devicetree
<nickchan>
since the p/e core pairs acts as logical cores that suddenly have their cache resized
<nickchan>
depending on the p-state
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<nickchan>
maybe just taking the pcore value is fine? to stay consistent with the frequency adjustments
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<nickchan>
caches are not gonna be in tomorrow's v2 just because of a10
<nickchan>
i will post them seperately later
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<f87>
I was considering the possibility of working on a rust xHCI USB stack (partly for m1n1 reasons but also personal interest)
<f87>
Is anyone already working on such?
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<opticron>
I know it's been mentioned off-hand as a nice to have eventually, but I don't remember anyone having actually started on it. I don't see it on the yak shaving wiki page, either. (I'm not an authoritative source on anything)
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<f87>
fair, it's not something i'm going to apply full time effort to but it's a nice backburner project
<f87>
(if usb can ever be considered 'nice')
<nicolas17>
yak shaving page needs more entries imo
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<nicolas17>
maybe someone wants to help and the low-priority nice-to-have item in the list is the one they have knowledge/experience with
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<jannau>
f87: rust xHCI + dwc3 driver + usb storage are required macos style "external" boot support. for asahi that would allow chainloading 2nd stage m1n1 from external media
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<nickchan>
the 50ms delay in the wdt driver isn't enough on some old socs i have tested
<nickchan>
i should do some experiments to increase the limit
<nickchan>
and by not enough I mean the reboot failed messages shows then the system resets
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<nickchan>
a7 takes about 105-110 ms to actually reset
<nickchan>
gonna make it wait 150 ms just to be safe
<nickchan>
will test newer ones too but i think the older the soc is the slower it is
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<nickchan>
a8 is worse
<nickchan>
takes 130-135 ms to reset
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<f87>
jannau: *nods* thanks for the heads-up re: dwc3
<nicolas17>
jannau: could you add it to the yaks page, if you agree it should be there?
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<nickchan>
okay a8 is the worst it seems a8x is slightly faster
<nickchan>
and the 16k devices that i have reseted in 80ms
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<nickchan>
ill call it 120-125ms max
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<nicolas17>
but where is 120-125ms pro
* nicolas17
goes back under his rock
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