ChanServ changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
<phire> oh this is cool, I can see it sending the gpu_va and size of my userspace allocations to the gpu firmware
<phire> probally a cache flush or memory clear command
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<alyssa> :'D
<phire> but this communication protocol is a bit weird
<phire> it writes the VA to gfx-handoff+0xa0, the size to +0xa8 and then writes 2 to 0x98
<phire> then somehow the gpu firmware knows to read that shared memory
<phire> then I think an interupt comes back and the cpu sets gfx-handoff+0x98 back to 0
<phire> I need to work out how to trace interrupts
<alyssa> phire: Naively, I would assume Apple uses ASC messages in place of direct interrupts
<alyssa> (Of course ASC fifo non-empty is an IRQ but Abstraction)
<phire> there is very little traffic going across the gpu firmware's ASC
<phire> it's bugging me
<alyssa> Hmm
<alyssa> to confirm you're looking both sgx and gfx-asc together?
<phire> sgx has even less register traffic than gfx-asc
<alyssa> Curious
<phire> and it's only reads
<alyssa> right :|
<alyssa> we're certain gfx-handoff is ordinary shared memory and not somehow special / MMIO?
<phire> It's possible the firmware gets an interrupt every time there is a write to it
<phire> but I do think it's real memory
<alyssa> Alright
<alyssa> what is the ASC traffic, then?
<phire> gpu sometimes sends 0x43 on EP20
<phire> cpu sometimes sends 0x83 with a 8bit value on EP21
<alyssa> what endpoints are those?
<phire> I don't have names for them
<alyssa> mind pastebinning the output of `ioreg -l`?
<alyssa> booted into linux right now
<phire> ha, I saved a copy of that
<alyssa> forgot how thick it is
<phire> also, this is the M1N1 trace acound the gpu allocation stuff: https://gist.github.com/phire/9cad6e6bbe4add5f8f9dcc55d5a03dbc
<phire> and the corrosponding wrap trace: https://gist.github.com/phire/adaa5fe1410678ae7d5f46cadeb8b259
<alyssa> hm i thought ioreg had endpoint stuff, boo
<phire> might be somewhere else?
<alyssa> phire: that's a lot more ASC traffic than you made it sounds like ;)
<phire> the stuff at the top is just re-initilization. I think it happens whenever the gpu is bought out of sleep
<alyssa> the 0xdead writes are ominous ;-p
<phire> besides, I'm mostly talking about entropy wise
<phire> might be because this is a debug kernel
<alyssa> sure
<alyssa> I just mean that every time the CPU sends the FW an ASC message, that's an opportunity for the ASC to check gfx-handoff, right?
<alyssa> er.. are gfx-handoff writes traced here?
<phire> (unknown, offset 0x10ffffb4nnn) are gfx-handoff
<alyssa> aaaaa
<alyssa> okay yes i see V_V
<phire> the asc traffic itself is mostly just <ep:20 0042000000000000, >ep:21 0083000000000000
<phire> if you clear the value at gfx-handoff+8, the kernel does the following panic:
<phire> panic(cpu 4 caller 0xfffffe0013c5d848): UAT PPL 0xfffffdf030af4160 (IOUAT): Invalid microPPL magic value found in the handoff region. Expected: 0x4b1d000000000002, Actual: 0x0
<phire> I admit, things would make much more sense if gfx-handoff was an mmio region
<alyssa> sven: ^^
<alyssa> https://googleprojectzero.blogspot.com/2020/07/ came up in two google searches in a row
<phire> seems to be memory, it holds any writes
<phire> (it's also located in physical memory)
<phire> the cache coherrency protocol could theortically tell the gpu firmware that memory has been updated, but that's a really janky hack
<alyssa> the table there is kinda interesting
<alyssa> 0x239028000, 0x4000, 0x4007, 'DART' ; dart-usb
<alyssa> 0x267030000, 0x4000, 0x4007, 'DART' ; dart-ave
<alyssa> 0x8FC3B4000, 0x4000, 0x40004016, 'GUAT' ; sgx.gfx-handoff-base
<phire> I think that just comes from ADT
<alyssa> I meant darts being grouped with the handoff
<phire> there are also carveouts there
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<baddek> a b o u t 9 m `il तi o n - iहr a ह`q i l o s t ` thल e i r li`ल vलes e i th e r be ca uz . o f di्r e ct ameri`can vi्ol e`nce ` and .. .beca uz /of si ्e`ge . u दs दa ma de . a`g दa iदn s t i दrद aद q t h at pr eदveद nt ed iद r aद qi f or m es se nt ial ` l i v i n g ` ma
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<phire> Weird... the only interrupt actually in use across both /arm-io/sgx and /arm-io/gfx-asc is the asc interrupt
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<alyssa> A very sleepy Alyssa is about to stream M1 GPU driver dev ^^
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<Tramtrist> 😻
<alyssa> okay, I think OBS is reconfigured
<alyssa> (...so sleepy)
<matthewayers[m]> Is there a link to the stream?
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<alyssa> ☁️ On air - https://twitch.tv/asahigpu ☁️
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<phire> Hey, this page table is actually 3 layers deep, and points at real-looking data
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<phire> ok... gpu-region is the context table
<phire> contains pointers to the page table for each context
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<alyssa> 🎉
<phire> the other page table (at gfx-shared-region + 0x10) might be for context -1, which shows up in logs
<alyssa> context -1, hm
<phire> yeah, we can probally ignore that for now. right now I want to know how userspace command lists get executed
<alyssa> *nod*
<alyssa> On Mali it's as easy as "write an address to a register and write the START command to the command register"
<alyssa> I imagine AGX has a lot more indirection.
<phire> My current theory is that there is some kind of memory structure with a list of command lists
<phire> and you send a message via ASC to tell it which one to execute
<alyssa> that would be guess, yes
<phire> with the amount of entropy I've got, that's the best susgestion
<phire> that structure must be global, since the ASC message doesn't have a context id
* alyssa nods
* alyssa should get back to coding instead of randomly perusing gitlab idly
<phire> This is probally another thing where there are registers on the sgx interface that control all this, but there is an ASC firmware in the middle
<alyssa> nod
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* alyssa powers the mac back on
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<alyssa> i must say it'll be nice finally having 3D accel on linux
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<alyssa> okay i swear i'm starting again i'm just real good at not doing things
<alyssa> ...and we're back https://twitch.tv/asahigpu
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<Tramtrist> wow .. i went grocery shopping and came back.. and you're still going at this pace.. quite amazing
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<phire> the gfx-shared-region + 0x10 page table is actually a L2 leaf, that gets inserted to cover the range starting at 0xffffffa000000000
<phire> and the only address that gets sent over ASC (which must be our control structure) is 0xfa0000b0000
<phire> this pagetable also maps IO registers into it
<phire> 0xffffffa010000000-0xffffffa010003fff -> 0x404d00000
<phire> that is the sgx's register range
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<phire> it also maps in some ranges I don't reconise: 0x20e100000, 0x28e494000, 0x204d60000, 0x200000000, 0x201000000, 0x202000000, 0x203000000, 0x204000000, 0x205000000, 0x206000000, 0x207000000, 0x2643c4000, 0x28e3d0000, 0x28e3c0000
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<Tramtrist> i was amazed at everything you were doing there alyssa from the dev environment on up
<Tramtrist> inspiring really
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