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05:23
<
phire >
good news: I have the "control struct", I can easily read memory, I can monitor changes to it
05:23
<
phire >
bad news: The amount of infomation changing in this control stuct is still a bit limited
05:24
<
phire >
an 8bit value that counts up, and what might be the lower 32bits of a VA address
05:25
<
phire >
(16kb aligned)
05:26
<
phire >
I might have to monitor all changes to the entire (mapped) gpu va space
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<
phire >
Or... I should expand the monitoring area
05:55
<
phire >
ffffffa000031f20 534b5452 4b434154 534b5452 4b434154 534b5452 4b434154 00000001 00000002
05:55
<
phire >
ffffffa000031f00 00000001 00000001 00000000 00000000 00000000 4b430000 534b5452 4b434154
05:56
<
phire >
Thats RTKSTACK repeated
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07:03
<
phire >
GFX Tempest-ASC4.1 FW cold booted! (Jan 11 2022 20:36:18)
07:03
<
phire >
G13 Firmware initializing
07:03
<
phire >
Build variant: X
07:03
<
phire >
Build version: B0
07:04
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07:05
<
phire >
WARNING: Waiting for space to add statistics! Consider resizing buffer or adjust interrupt heuristics
07:11
<
sven >
phire> Thats RTKSTACK repeated <-- sounds like that's also how the firmware and RAM of the co-processor is mapped then
07:12
<
phire >
I think this area that I'm seeing changing is the firmware's heep, or stack
07:12
<
sven >
yeah, sounds like it
07:12
<
phire >
big 0x88000 byte region
07:13
<
sven >
there's a segment-ranges property in the ADT that usually contains the mapping for the firmware fwiw
07:14
<
phire >
This is an address that has been mapped in via UAT
07:14
<
phire >
I think it's actually CPU controlled
07:15
<
phire >
how do I decode segment ranges?
07:15
<
sven >
usually the CPU needs to map in the firmware for most of these co-processors. it's usually just already done by iBoot fwiw
07:15
<
sven >
erm, let me check. but iirc it was just a list of u64s (paddr, size, iova) or something similar
07:15
<
phire >
well, something is responding to ASC messages on boot, I assume that's the firmware
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<
phire >
slightly annoying for writing a driver, we will have to understand and recreate this initilzation struct to make the firmware happy
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<
sven >
just be glad you didn't decide to look into DCP instead. that thing's full of magic structs from what i can tell
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09:04
<
phire >
wait... this might actually be single four level page table
09:04
<
phire >
with only two entries in L0
09:07
<
phire >
If so, the gpu firmware has already initilized a bunch of page tables. Some of them point into phyisical memory
09:07
<
phire >
quite a few of them, actually
09:31
<
phire >
oh, it's the firmware from iboot
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18:38
<
marcan >
phire: don't get confused by all the ASC side junk
18:38
<
marcan >
yes they have page tables and data sections and the code is readable too
18:38
<
marcan >
but you don't care about any of that
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<
sven >
sounds like it maps those with thus UAT iommu as well, which also makes sense I guess
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23:09
<
phire >
marcan: yeah, the UAT iommu is "unified" and covers the ASC stuff (at 0xffffff8000000000) and the gpu allocations from userspace (useally at around 0x1500000000)
23:10
<
alyssa >
no way that could go wrong ;-p
23:12
<
phire >
yes, I raised my eyebrows when I realised that. The pagetages controlling the 0xffffff8000000000 range get mapped into UAT too
23:13
<
alyssa >
no way that could go wrong ;-p
23:20
<
phire >
marcan: how would you feel if I had to RE the AGXG13X kext? Because I'm really lost and not finding the communication channel that gpu work is submitted over
23:21
<
phire >
I'm supicious the comunication channel is simply not listed in ADT
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