#asahi on 2021-10-25 — irc logs at oftc.irclog.whitequark.org

2021-08-23 06:15 marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-stream #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi

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00:03 <mini> I hate buying that kind of thing from amazon these days, knowing if you're getting something that even vaguely meets the spec is practically impossible :(

00:03 <mini> I have a handful of relatively trusted brands I'll go for and that's it

00:04 <mini> fwiw, I've been using cablematters USB-C -> DP cables, and an amazonbasics HDMI for 4k60 and haven't had any problems with that for M1

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06:33 <remanifest> Just came here to say I'm so happy to see that people are working on this! What skillsets do you guys need at this point?

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08:13 <jn> remanifest: curiosity is the most important trait we need :) but beyond that, kernel developers can always find something to do, and perhaps someone who would read the wiki and update it where necessary

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09:17 <chadmed> i think maybe alyssa could use some help with graphics? its such a huge undertaking for one person

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13:01 <_jannau_> apple is faster than planned. my macbook pro is shipped with an expected delivery date of thursday. initial window was friday to tuesday

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13:27 <robinp_> my local Apple store originaly told me that store stock would be available Friday, but today they told me Wednesday (I just hope there is no queue)

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13:31 <robinp_> whats the command to use img4tool - trying with img4tool -e -p j274.bin DeviceTree.j274ap.im4p - but it fails to extract ?

13:36 <marcan> mine is supposedly arriving friday

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13:36 <marcan> robinp_: -e DeviceTree.j274ap.im4p -o j274.bin

13:37 <marcan> the -m -p thing is for breaking up an img4 into im4p and im4m

13:39 <kettenis> function-spi_en = 119:GPIO(0xc3, 0x10101)

13:39 <kettenis> do we have an idea what the 0x10101 there means?

13:39 <robinp_> marcan: ty

13:41 <_jannau_> anandtech article is up, CPU memory bandwidth seems to be "only" ~240GB/s over all 3 clusters, ~100GB/s for a single core

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13:43 <marcan> 100GB/s for a single core sounds like just how fast the CPU can copy

13:43 <marcan> seeing what I saw on the M1 vs CPU freq

13:53 <j_ey> kettenis: how is the progress? (dunno what 0x10101 is)

13:58 <kettenis> not getting any reply from the keyboard over spi

13:58 <kettenis> :(

13:59 <j_ey> :( hopefully soon!

14:00 <j_ey> have you tried to use te gpio tracer? might help to compare

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14:03 <kettenis> you mean using run_guest.py?

14:03 <j_ey> yeah

14:03 <j_ey> and either compare to macos or linux

14:03 <mini> it does indeed beat a 5800X quite nicely then...

14:04 <kettenis> j_ey: no, so far I haven't used it

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14:07 <j_ey> it doesn't show timings, but it might at least show if youre toggling some bits in the wrong way/order

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14:55 <nsklaus_> povik: is there any place i could consult to follow your progress on the sound driver ? your github account maybe, if you have one ?

14:56 <nsklaus_> or twitter, gitlab, anything ?

14:56 <j_ey> marcan: and you complain about gpio_gpio: apple_pmgr_reset_reset :P

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15:00 <maz> j_ey: at least it is a noun followed by a verb (or the other way around).

15:01 <j_ey> maz: let me poke fun!

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15:09 <robinp_> 12.0.1 is out now (or has it been for a while - I only just noticed it...)

15:09 <j_ey> out out, or beta?

15:09 <robinp_> I thnk out out

15:10 <robinp_> it was meant to be 10am PT

15:10 <robinp_> which I think is about now

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15:14 <robinp_> can anyone else confirm - I hope I'm not downloading the RC...

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16:23 <agraf> kettenis: you do OpenBSD things, right? https://github.com/utmapp/UTM/issues/3197

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17:13 <marcan> j_ey: but that's a noun and a verb! totally different!

17:14 <marcan> oh maz said the same :D

17:14 <marcan> maz: I think we're pretty much good on the pinctrl bindings, do you want to re-send the DT changes with the apple,npins change?

17:15 <kettenis> agraf: yes I've seen that

17:15 <kettenis> it works on real hardware though

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17:24 <maz> marcan: sure, I'll do that either later today or tomorrow morning, depending on how annoyed I'm in this call...

17:24 <marcan> ah :)

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17:25 <j_ey> robinp_: news sites suggest 12 is out

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17:33 <kettenis> so the the SPI CS line is actually active low

17:33 <kettenis> that isn't obvious from the corellium kernel...

17:34 <kettenis> with that fixed, I can turn the caps lock led on :)

17:34 <j_ey> kettenis: !

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17:38 <marcan> isn't CS usually active low?

17:39 <kettenis> it is

17:40 <kettenis> but the gpio flags in the DT are 0, which means active-high

17:42 <j_ey> weird

17:45 <kettenis> j_ey: you have been using the correllium spi/keyboard driver with your new pinctrl driver?

17:46 <j_ey> yes

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17:47 <j_ey> kettenis: https://github.com/torvalds/linux/blob/master/drivers/spi/spi.c#L2685

17:50 <kettenis> sure, but the spi-apple-mc.c driver seems to manage the CS on its own

17:50 <j_ey> hm true

17:51 <j_ey> (I was playing around with refactoring it to use more of the core spi stuff)

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17:53 <maz> kettenis: agraf: Page D4-2652 in version G.b of the ARMv8 ARM explicitly calls out CMOs on device memory as allowed.

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18:07 <kettenis> maz: so for some reason Apple's hypervisor framework traps on those

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18:33 <agraf> maz: what is it supposed to do on device memory? Or in other words: What AXI message does it translate to?

18:34 <agraf> Or is it supposed to just be a NOP?

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18:53 <maz> agraf: it is supposed to do what it says on the tin: a cache clean and invalidate to the PoC. the end-point is allowed to barf, but the instruction is still valid.

18:53 <maz> kettenis: who cares? :D

18:54 <agraf> maz: Sounds like it's the core / cache's responsibility to deal with this instruction then rather than the device. I don't remember any AXI message that would even remote know anything about cache ops.

18:55 <agraf> (which is good news, it means in this context it's just a nop)

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18:57 <maz> nobody says anything about AXI. the only mention of AXI in the architecture is as follows:

18:57 <maz> "This means the

18:57 <maz> mechanisms by which different memory type and Cacheability attributes are presented on an interface to an

18:57 <maz> interconnect fabric such as AMBA ® AXI are, strictly, outside the scope of the architecture."

18:58 <maz> as far as the core is concerned, this could be CMO over avian carrier.

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19:08 <agraf> maz: I'm mostly trying to understand where in the abstraction levels this would usually be cut off. Theoretically, a DATA exit to QEMU is on a pretty similar level to an AXI message on a real core.

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