ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
<dschuermann> it would automagically prevent sinking instructions out of loops (unless invariant) and such
<jekstrand> It'd require a bit of special-casing but, TBH, might not be a bad idea.
<jekstrand> non-LCSSA is a bit of a lie when you think about things in terms of waves.
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<jekstrand> (which is why it's required for uniformity analysis)
<dschuermann> and that also blocks making it metadata ;)
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<anholt> airlied: looks like 75ef5991f5af06997551dabc053300261e32ca40 just caused fails in lvp due to slt being unimplemented.
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<airlied> anholt: never seen any fallout from that one
<anholt> it just appeared in my rebase
<airlied> 0cf25f559f8dc99d59637e74650c38d6428433f3 has caused me some wierd regression in spirv cts test
<airlied> anholt: got a pointer, I've ran cts master here recently and didn't see it (or maybe I completely missed it)
<anholt> dEQP-VK.spirv_assembly.instruction.compute.float16.arithmetic_3.step fails
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<airlied> oh I should rebase mesa and check that later
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<airlied> anholt: lower_scmp should lower that though shouldn't it?
<anholt> would have thought
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<anholt> boo. down to a 27% perf win on this testcase after doing src_is_const not src_is_dynamically_uniform
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<anholt> jekstrand, dschuermann: could one of you give a quick example how nir_src_is_dynamically_uniform would go wrong without lcssa? would love to get it documented.
<jekstrand> anholt: Say you have a loop with a single non-uniform exit.
<jekstrand> anholt: If you then have something declared inside the loop which is uniform within the context of a single loop iteration but which leaves the loop, it will show up uniform outside the loop.
<jekstrand> However, because the loop exit was non-uniform, it might not actually be a uniform value when considered outside the loop.
<jekstrand> LCSSA fixes this because nothing is alowed to exit the loop without going through a phi unless it came from outside the loop to begin with.
<jekstrand> We can then analyze that phi and see that it's associated with a non-uniform loop exit and mark it accordingly.
<Lyude> jani: i haven't had the time to look at it but i trust y'all, i'm mia right now unfortunately
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<idr> airlied, anholt: Before that commit, it would have gotten SGE instead, so... weird?
<idr> Maybe because it's marked 'exact'?
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<imirkin> jenatali: sadly not a failure mode i've personally seen before
<imirkin> (or perhaps happily?)
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<jenatali> imirkin: Fair enough. Thanks anyway. I'll let you know when I get to the bottom of it
<jenatali> But that might be a while
<imirkin> jenatali: if you want to find the first failing draw, i've found retracediff (part of apitrace contrib scripts iirc) to be extremely helpful in tracking down where these issues start happening
<imirkin> oftentimes the problem has nothing to do with the enabled feature
<jenatali> I've gotten pretty good at debugging this kind of thing
<imirkin> ah cool
<jenatali> This is my third mapping layer to D3D12 lol
<imirkin> ... and i hear three times is a charm
<airlied> idr: yeah might be the exact marking, seems like a few drivers won't be expecting slt though
<imirkin> (unless you're joe pesci, in which case 6 times is a charm...)
<airlied> lvp isn't the only driver setting lower_scmp
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<idr> I thought iris did too, and it's surely not expecting slt.
<airlied> indeed it does, wierd
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<HdkR> FLHerne: Do you know of a maintainer of Alpine btw? I've noticed that the SDL2 package is broken when using cmake
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<airlied> idr: exact shouldn't matter though, the lowering show always happen, wierd
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<airlied> idr: seems like it's a bit size problem, but no idea why other drivers aren't hitting
<airlied> jekstrand: you understand opt_algebraic don't you :)
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<idr> Lemme guess... 16-bit?
<airlied> idr: yeah for some reason the slt expression isn't getting matched for16-bit
<idr> That is... weird.
<idr> Why would that only impact lp?
<airlied> does anyone else support 16-bit?
<idr> There's something fishy here.
<idr> That's possible.
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<idr> Do you have a specific test case that's failing? I can poke at it tomorrow.
<airlied> dEQP-VK.spirv_assembly.instruction.compute.float16.arithmetic_3.step
<airlied> on lvp
<airlied> it looks like the slt lowering isn't getting applied due to 16-bit, but one look at nir_*_algebraic doesn't make me understand why :-P
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<airlied> idr: b2f16 doesn't appear to be a legal opcode
<airlied> hmm maybe it is
<idr> I tried that as an optimization, but, if I recall correctly, it generated identical code on Intel GPUs.
<airlied> idr: yes that passes
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<jenatali> Out of curiosity, is there some known set of apps that handle context reset through the robustness extension?
<jenatali> I'm wondering if it's worth my time to try to make it actually work
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<idr> airlied: Okay... If I can't find something obvious in the morning, I'll send that patch as an MR.
<idr> I'll take you and anholt on whatever I end up with.
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<HdkR> How much would people fight me if I wanted to create a Metal frontend for Mesa? :D
<jenatali> HdkR: Seems more practical than glide
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<HdkR> jenatali: I wouldn't discount how many more people would like glide than Metal. I'll discount potential future work that I do, not linkmauve's :D
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<jenatali> Sorry, didn't mean for that to sound critical, I think both are great. Just seems like Metal would maybe light up even more apps
<airlied> HdkR: is this to run apple store games?
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<airlied> HdkR: I assume it would be Metal on Vulkan
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<airlied> HdkR: also you have to call KVnetlom
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<HdkR> airlied: Nah, I don't care about apple store games. Just think the API is nice and I would love using it on Linux with the metal-hpp bindings
<airlied> HdkR: you could go nuts and write metal drivers for each gpu, but metal on vulkan would like provide more success
<HdkR> As far as I'm aware the API has some features that Vulkan can't directly translate
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<HdkR> Like bindless pointers
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<HdkR> So if it was wired in to Gallium it would have the highest likelyhood of not breaking horribly :D
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<DrNick> Direct3D had some features that Vulkan can't directly translate
<DrNick> Like geometry shaders
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<airlied> HdkR: I think metal would be too lowlevel for gallium, so a vulkan + exts model might be better
<HdkR> hmmmm
* airlied assumes metal is cmd buffer not ctx based
<HdkR> But then the problem would be that I'm terrible at Vulkan
<HdkR> and that's a major hurdle to overcome :D
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<imirkin> jenatali: chrome might? not sure.
<imirkin> (re caring about context resets)
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<HdkR> Oh hey, I finally found out why I was getting chrome hangs. Apparently I enabled their Vulkan renderer
<HdkR> Oops
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<jekstrand> HdkR: RE: Metal. I wouldn't stop you but I also don't see much point.
<HdkR> Pointless things, I specialize in those
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<airlied> just do a metal on gallium on llvmpipe layer for extra pointlessness
<Sachiel> leadpipe
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<jekstrand> If you did it on gallium then you could use alyssa's M1 work to replace Apple's native Metal. (-:
<airlied> yeah it would be horrible on gallium, so would be only be useful in an llvmpipe only way
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<airlied> HdkR: is there any sort of metal test suite?
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<HdkR> airlied: Doubt, and I bet they would be all written in obj-c++2.0 or w/e the original language was
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<dschuermann> anholt, jekstrand: I just looked up the nir_src_is_dynamically_uniform function. it should be renamed to *_is_statically_uniform. no dynamic involved, and thus, should be fine without lcssa.
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<whald> hi! when doing a gbm_bo_map with GBM_BO_TRANSFER_WRITE, is it expected to see _isl_memcpy_tiled_to_linear_sse41 in the stack trace, burning quite a lot of CPU time? i intend to write to the mapped region only and was only expecting to see the _isl_memcpy_linear_to_tiled happening in gbm_bo_unmap. (this is on Intel iris)
<whald> so basically I was expecting GBM_BO_TRANSFER_READ -> expensive map, cheap unmap -- GBM_BO_TRANSFER_WRITE -> cheap map, expensive unmap -- GBM_BO_TRANSFER_READ_WRITE -> expensive map & unmap
<Kayden> I believe that's expected
<Kayden> I don't know about gbm map semantics specifically, but...that maps through the various layers to iris_transfer_map()
<Kayden> the thing is, just because you map something for writing, doesn't mean that you guarantee you're going to overwrite the entire region you mapped
<Kayden> so we have to read the existing data into the temporary area, let you write there, then write it back to the original
<Kayden> usually there's a flag like PIPE_MAP_DISCARD_RANGE or GL_MAP_INVALIDATE_RANGE_BIT which says "by the way, you can throw out the exsiting contents"
<Kayden> but I don't see any such flag in the gbm api
<MrCooper> Kayden: GBM_BO_TRANSFER_WRITE would be pointless if so (could be dropped in favour of GBM_BO_TRANSFER_READ_WRITE)
<whald> Kayden, I had an discussion here about the exact topic, but for amdgpu, and there the conclusion was the when mapping a region for write means I *have to* write the whole region. I was getting rendering artifacts when I did not.
<Kayden> that's fair, maybe that's the semantics gbm should be following
<whald> MrCooper, indeed I do not understand what's the point of these flags the way it's implemented on intel
<Kayden> it's not really an intel thing though
<Kayden> dri2_map_image turns these into generic gallium maps and passes no such flags
<Kayden> so IMO that's a gallium dri2 frontend bug
<Kayden> the other APIs that translate to those same gallium hooks allow partial writes
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<Kayden> seems like http://whitecape.org/paste/mapimage.txt or something similar would do the trick.
<whald> Kayden, this is a patch against current mesa?
<Kayden> yeah
<whald> Kayden, you came up with this *this fast*?
<Kayden> (just typed it up, haven't tested it at all)
<whald> Kayden, looks like it may work, I'll give it a spin and report back. thanks a lot!
<Kayden> :) nice!
<Kayden> thanks!
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<Kayden> off to sleep, good luck!
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<whald> Kayden, this works perfectly for me
<whald> (with Kayed off to sleep, should I report a bug somewhere so this won't be lost?)
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<pq> whald, yeah, an issue in Mesa Gitlab, or maybe even a merge request.
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<whald> pq, I opened https://gitlab.freedesktop.org/mesa/mesa/-/issues/6020 but did not want to submit Kayden's work under my name
<pq> that's fine :-)
<pq> forwarding patches is also fine if you know you are allowed to forward them, patch author can be different from patch submitter.
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<javierm> whald: you can commit with their authorship with the git-commit --author option
<whald> javierm, pq, ok, I'll open a PR then. hope my git foo is strong enough not to mess this up ;)
<whald> ehm, not so fast, using "Kayden from IRC" is not what I should use for the author, I guess?
<pq> indeed
<emersion> you can grab the info from the git log
<pq> in irc you can check /whois kayden to see if they set their real name. If they are regulars in the project, you can probably find them in the git history by that so see what they as Author.
<pq> *use as Author
<pq> heh, wish I remembered that page
<whald> oh, thanks, then I'll open the PR. thanks again!
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<pq> personally I would confirm with the person with if it's ok for me to forward the patch, unless you're sure it's ok
<emersion> probably fine to open the MR and ask for an ACK in the description
<whald> huh, then I guess I'll skip the PR part for now.
<linkmauve> HdkR, I’ve actually got feedback that people want to use this driver once it is usable, which I didn’t expect!
<whald> something else: is there some API I could use to do the work done (swizzeling?) in gbm_bo_unmap myself? I'd like to implement a few formats I care about and fall back to the GBM approach for stuff I have not implemented
<pq> whald, why do you think that is a good idea?
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<HdkR> linkmauve: Build it and they will come!
<pq> whald, gbm_bo_map could use the GPU to do the conversion during the copy without bothering CPU that much, and direct CPU access to the original buffer could be slower than having the GPU copy it.
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<pq> whald, I would guess the reason intel uses the CPU directly is that the CPU access to the original buffer is fast, since it's "just" sysram. Dedicated VRAM (discrete cards) is likely a very different story.
<whald> pq, because the memmove to the scratch buffer is taking almost as much time as what's happening in gbm_bo_unmap. i imagine to cut that time in half when skipping yet another scratch buffer.
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<whald> pq, indeed on intel, with GBM_BO_USE_LINEAR, map + unmap are basically free. with GBM_BO_USE_RENDERING, unmapping takes quite some time.
<pq> whald, I'm not sure I undertand, but if you intend to never run on any other machine, then sure. ;-)
<whald> pq, OTOH, on Intel the actual rendering (on GPU) takes a hit when using linear FBs. I'd like to have fast BO updates and fast rendering.
<whald> pq, I'd like to have it run wherever possible but we have a limited set of hardware we actually ship and if I can get some more performance out of those that's probably worth the effort.
<pq> whald, and the developers of GBM didn't care? ;-)
<pq> if you find something sub-optimal, why not try to fix it upstream to benefit everyone? Or is it the very API design that is holding you back?
<whald> pq, I assume they did care, but I assume taking the burden of supporting different FB layouts off the user is part of the purpose of GBM, so there's the scratch buffer in place (at least for Intel + GBM_BO_USE_RENDERING), which i'd like to skip. :)
<whald> pq, we absolutely submit upstream whatever we come up with, but here I indeed the API does not support what I intend to do. or I'm missing something. that's why I ask. :)
<pq> so instead you would use the scratch buffer in tiled format?
<whald> pq, I think I would want to have no scratch buffer at all to save the memory bandwidth.
<pq> but then what about discrete cards?
<pq> the kernel UAPI for mmapping buffers directly exists, btw. so you can try to get a raw map if you want.
<pq> but for a program that is supposed to run on more than one model or vendor of GPU that can easily backfire
<whald> pq, so when I known I can "do it", I could mmap the BO FD and write swizzled data there?
<pq> I believe so - obviously I've never tried for non-linear buffers
<whald> pq, wouldn't this just mean to check the BO modifiers, decide I have implemented my "fast path" for those and otherwise go the bo map/unmap route?
<pq> yup, assuming the mmap does not have driver-specific behavior
<whald> pq, then I guess there's only one way to find out! ;-) thanks for the input!
<pq> ISTR some hardware having blocks that can give the illusion of a linear mmap, but these blocks are scarce.
<pq> you also have the problem that a direct CPU mmap can be slower to access than a copy in both directions, but when that happens I can't really say
<whald> pq, I played around with this some time ago and noticed that GPU -> CPU transfers on amdgpu are very slow, the other way around it's fast. on Intel both are fast. but I care about writing only, so maybe I'm lucky.
<pq> if you work like a game, you're on the sweet path, I guess :-)
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<javierm> tzimmermann: Andy suggesting me to use a macro that haven't even landed in mainline yet is a next level of bikeshedding that never experienced before :)
<tzimmermann> :)
<tzimmermann> i think the format helpers are fine
<javierm> yeah, agreed
<tzimmermann> we can optimize performance later, if necessary
<javierm> tzimmermann: as mentioned in the ML I think that's important to think about readbility and robustness, maybe even more than performance
<javierm> I spent a non-trivial amount of time wrapping my head around the format helpers
<tzimmermann> :)
<javierm> tzimmermann: do you have any more concerns about the driver?
<javierm> tzimmermann: I think that will just go ahead and address the last comments from Andy to post a v5 later today, but will wait if you plan to take a look
<tzimmermann> let me check quickly...
<javierm> tzimmermann: thanks!
<tzimmermann> javierm, there was one thing in patch 3
<tzimmermann> javierm, and one in patch 2
<javierm> tzimmermann: gotcha. Just read your comments, thanks
<tzimmermann> yw
<tango_> feel free to redirect me to the best place where to report this. I'm using the amdgpu driver and since at least kernel 5.15.something every time anything tries to access /dev/kfd I get a dmesg spam to the tune of:
<tango_> kernel/workqueue.c:3094 __flush_work.isra.0+0x20e/0x220
<tango_> the WARNING: always refers to the same source line, although obviously the CPU and PID change
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<tango_> (example: http://sprunge.us/cjmLTD)
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<javierm> tzimmermann: is this what you meant? https://paste.centos.org/view/raw/8cd6a3b7
<tzimmermann> javierm, not quiet. it could still happen that you enable the pipe with a virtual screen and have to adjust the view accordingly. best copy the rsp code from simpledrm's pipe_enable
<tzimmermann> javierm, but do we really clip here? hmmm....
<javierm> tzimmermann: I use drm_rect_intersect() in the pipe update callback but maybe that's not needed as well ?
<javierm> I use the shadow buffers bigger than display virtual screen support so I guess for update is correct to use that ?
<MrCooper> tango_: https://gitlab.freedesktop.org/drm/amd/-/issues (check for an existing report first)
<tango_> MrCooper: thanks
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<tzimmermann> javierm, i just checked your driver and that example link. what you do should be correct.
<javierm> tzimmermann: cool, thanks for the confirmation
<tzimmermann> sorry it's friday afternoon here...
<javierm> tzimmermann: no worries. I'm reaching my level of understanding about DRM buffers handling so I preferred to confirm before sending a wrong v5 :)
<javierm> tzimmermann: thanks a lot for all your feedback and patience for the explanations
<tzimmermann> but i wonder if simpledrm gets it right. that has to wait until monday
<bbrezillon> does anyone know if it's allowed to load a texel from a VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE descriptor (access the sampled-image without its sampler)?
<bbrezillon> oh, forgot to add the 'on a cube image view' constraint
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<bbrezillon> the reason I'm asking is that d3d12 doesn't allow loading a texel from a cube texture (textureLoad() doesn't work on cube SRVs), and if we need to support that case, that implies adding SRVs resources exposing cubes as 2darrays
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<bbrezillon> we do that cube -> 2d-array lowering for storage images, but that one is easier, because we know the resource will never be sampled from, so we can drop the cube image and replace it by a 2Darray. But if sampled-images need to support both txf and tex, we need to duplicate the resource and pick one or the other depending on the texture instruction
<bbrezillon> jekstrand: ^
<jekstrand> bbrezillon: Vulkan has no such restriction.
<bbrezillon> that's what I thought. Oh well, I'll add those cube-as-2array descs then
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<jenatali> :(
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<agd5f> MrCooper, daniels: either give me maintainer privileges or add shashank as a developer for xf86-video-amdgpu?
<agd5f> *can you
<MrCooper> sure, sec
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<daniels> agd5f: you've got the keys to the kingdom
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<agd5f> woot! thanks
<ccr> phenomenal cosmic power! itty-bitty living-space.
<MrCooper> daniels: beat me by 11 seconds :P
<daniels> haha sorry
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<jekstrand> bbrezillon: I lied. It's not allowed:
<jekstrand> " Image must be an object whose type is OpTypeImage. Its Dim operand must not be Cube, and its Sampled operand must be 1."
<jekstrand> That's weird
<jekstrand> I thought it was
<jekstrand> Not sure why it's disallowed. I think it should work if you treat it as an array but I guess I've not tried.
<zmike> probably because it's disallowed in opengl too
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* alyssa trying to learn to dim intensifies
<bbrezillon> jekstrand: ok, that's good news!
<bbrezillon> jekstrand: BTW, any chance we could move forward with !14406 now that your vk_command_pool series has been merged
<jekstrand> bbrezillon: Yeah, I'll try to take a look soon. Maybe today.
<bbrezillon> cool!
<jekstrand> bbrezillon: I think you've got me convinced that it's not as terrible of an idea as it seemed at first. Also, dozen needs it for sure.
<jekstrand> The only question now is mechanics.
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<bbrezillon> jekstrand: and if you get bored, there's !12210 too :)
<alyssa> ...how many copies of the kernel does dim setup check out i'm so lost
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<vsyrjala> alyssa: i think 3 worktrees is the min: tip+rerere+whatever branch you want to work on
<vsyrjala> dunno how mnay it actually creates
<alyssa> vsyrjala: delight
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<alyssa> WARNING:BAD_SIGN_OFF: Duplicate signature
<alyssa> what's the correct sign-off ordering for "authored a commit (my sign off), reviewed by someone else (their r-b), pushed by me (my signoff)"
<imirkin> just one sign-off by you. sign-off = "patch passed through me"
<imirkin> it did not pass through the reviewer, so that doesn't count
<alyssa> does it go above the r-b or below the r-b?
<imirkin> doesn't really matter afaik. r-b is not a tag that is often used on kernel things
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<alyssa> ...?
<imirkin> (but maybe that's different in drm, not 100% sure)
<imirkin> the usual thing is that the maintainer picks up the patch from list, reviews, slaps their s-o-b on it, and pushes it further up the chain
<imirkin> alternatively if they want someone else to pick up the patch, they will ack it
<emersion> jani: thanks for fighting for readable code, really important IMHO
<imirkin> e.g. a patch which modifies things under maintainers 1 and 2, 1 will ack, 2 will s-o-b and push through their tree
<alyssa> arff
<vsyrjala> dim extract-tags slaps the rb/abs to the very end, so that's where i usually leave them
<alyssa> vsyrjala: stepri01 said to grab the tags from patchwork
<vsyrjala> if i manually apply some of them then i tend to put them ahead of my sob, so that commit -s doesn't double sob me
<vsyrjala> alyssa: if you want to use pw for that go ahead. i only use it to roughly keep track on what is still waiting for reviews
<alyssa> OK
<vsyrjala> for applying stuff i just feed patches straight from mutt to dim
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<alyssa> why does dim fetch sound-upstream?
<alyssa> why is dim-push-branch doing so much i'm so confused
<alyssa> i really hope i didn't just f*** up the tree
<vsyrjala> it builds a fresh drm-tip, which is a merge of all semi-relevant branches/trees
<mripard> alyssa: it's friday evening (or night) for all the maintainers, we won't notice before monday :)
<alyssa> i see my patch there
<alyssa> and i don't see it anywhere else so i guess i did it right
<mripard> it looks fine to me yeah
<alyssa> that was terrifying
* alyssa sure hopes she didn't just break a build or something somehow
<vsyrjala> yeah, drm-tip looks fine here
<vsyrjala> dim also has a dry-run knob if you want to it not to push stuff
<vsyrjala> though iirc it still says it pushes stuff, but actually doesn't
<alyssa> i don't understand where all those merge commits came from
<vsyrjala> dim rebuild-tip
<vsyrjala> it runs it automagically when you push
<alyssa> how did drm-intel get into it
<vsyrjala> it merges all the branches into drm-tip
<vsyrjala> nightly.conf in the rerere has the list
<alyssa> okay..
<alyssa> scary $#!%
<anholt> dschuermann: ok, that was my conclusion from reading it again this morning, too!
<anholt> will take care of it.
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<alyssa> vsyrjala: ok, and just pushed a bug fix to drm-misc-fixes
<alyssa> I don't see it in drm-misc-next, though .. when do those get merged?
<vsyrjala> the flow is documented somewhere. i always confuse mysefl with drm-misc*fixes though so i try not use them :P
<alyssa> (The patch fixes a bug affecting Linus's tree and all drm-* trees)
<alyssa> minor bug fix so I don't think it really matters but i thought-- nvm
<alyssa> (Minor in terms of # of affected platforms; in tree currently only arm hdlcd)
<alyssa> (On an affected platform it fixes a WARN on every swap..)
<alyssa> (IIRC)
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<mssx86> greetings, i'm on a i965 igpu (i5-3320m), building 22.0.0-rc2 tells me that classic i965 is deprecated. in that case should i go with i915 or crocus for the gallium driver?
<ajax> crocus
<mssx86> thank you for your response, i have xorg-server built with dri enabled, do i need to rebuild x's server after switching to gallium?
<ajax> nope
<kisak> i915g is intel gen 3, crocus is gen 4-7.5 (and a little of gen 8)
<mssx86> ajax: thanks a bunch, i appreciate it.
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<kisak> ^ in the context of mesa drivers, it's all i915 on the kernel side
<mssx86> kisak: my build for i915 just finished, was planning on doing crocus, should i not if crocus is for haswell and above?
<kisak> Haswell is intel gen 7.5
<mssx86> oh right.
<mssx86> going with crocus then.
<mssx86> will report back, i genuinely appreciate your responses, thnak you.
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<FLHerne> kisak: Intel (used to) brand processors as 'i7 gen 3' or whatever
<kisak> FLHerne: I'm aware of the difference between the cpu die generation and the gpu-sided generation
<FLHerne> where I think gen 1 was Nehalem, so Haswell would be 4 IIRC
<FLHerne> ok, but mssx86 wasn't :p
<kisak> fair enough
<alyssa> oops I think I accidentally became a kernel dev
<HdkR> oops
<alyssa> hate when that happens
<alyssa> sneaks up on you
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<jannau> more than an unnamed drm driver for cursed HW would proof?
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<airlied> alyssa: next is accidentally becoming a kernel maintainer
<alyssa> airlied: oh no
<alyssa> jannau: i'm pretty sure i named that driver "panfrost" ;)
<HdkR> Nice
<alyssa> not sure why it's butchering my name
<alyssa> oh
<alyssa> mb
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<gawin> someone knows cause of "InternalError (Unable to get sensible measurements for estimation at es2pShaderOperatorTests.cpp:718)" in piglit? (happens on vertex shaders a lot)
<linkmauve> alyssa, that happened to me the last time I bought a phone, and then I became a maintainer too.
<linkmauve> So weird how things just happen.
<alyssa> linkmauve: truly
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<alyssa> ok.. time to figure out how to make the panfrost blitter better
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<alyssa> jekstrand: if I need to solve a 3x3 linear system in a blitter [on the CPU, O(1) per blit] have i taken a wrong turn
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<alyssa> (If blitting with dst x,y != 0, need to compute varyings that interpolate to what we want.]
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<imirkin> alyssa: can you disable viewport transforms?
<alyssa> not meaningfully
<imirkin> alyssa: on nouveau, we do blits by disabling viewport transforms, so the coords are all the natural coords
<alyssa> i'm trying to implement blits with a special "full screen draw" primitives
<alyssa> Oh, the viewport transform is always disabled
<imirkin> ah i see
<imirkin> and no scissors i assume? :)
<alyssa> scissor doesn't help
<imirkin> and/or "window rectangle"
<alyssa> the issue is varying interpolation
* imirkin tries to remember how this is handled in nouveau
<alyssa> (Logically interpolating from (dst x, dst y), the hardware actually interpolates from (0,0) )
<imirkin> right
<alyssa> if blitting to a linear image, could play games with the pointers to make that physically 0,0
<alyssa> doesn't usually work for tiled and especially not compressed
<alyssa> then again i think for compressed images we have.. bigger.. problems..
<imirkin> in case you want to try to sort it out
<alyssa> Anyway, on paper I can solve the barycentric interpolation equations in software to compute what the coords should be
<alyssa> but Mesa does not seem to have any linear algebra utils and that should probably stay that way ;)
<imirkin> x0,y0 -> x1,y1 are the values used as the vertices of the drawn primitive
<alyssa> uh wait we do have util_invert_mat4x4 lmao
<alyssa> ..mesa/mesa/m_matrix.c, we have a whole linear algebra thing in tree, oof
<imirkin> doesn't mean you should use it.
<alyssa> Quite ;)
* alyssa wonders what the DDK does.
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<jekstrand> alyssa: Uh... Not sure.
<jekstrand> [6~
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