2022-12-21 00:45
ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<
HdkR >
How often is it expected that applications actually don't use XFree for the return of glXChooseFBConfig?
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<
HdkR >
I don't trust applications /not/ messing this up
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<
Kayden >
alyssa, gfxstrand: looks like 7f6491b76d51f35e76715275124d4a8d2eaf8db1 broke the build with -Dintel-clc=enabled (spir-v shaders fail to compile)
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<
Kayden >
trying to read through that patch to find the spot...
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<
alyssa >
Kayden: hooray!
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<
alyssa >
broke the build how?
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<
alyssa >
I don't know if I could build with intel-clc if I wanted to
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<
Kayden >
we're now getting mov(16) vgrf23+0.0:UQ, f0.0<0>:UW instructions where the destination is only 2
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<
Kayden >
64-bit destination where we're expecting it to be lowered to 32-bit I guess
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<
alyssa >
I know some of those symbols
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<
Kayden >
flag register being moved to a 64-bit temp register
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<
Kayden >
but the temp register is only 32-bit
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<
Kayden >
so something with booleans maybe
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<
alyssa >
- if (list_is_singular(&load_const->def.uses) &&
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<
alyssa >
- list_is_empty(&load_const->def.if_uses)) {
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<
alyssa >
+ if (list_is_singular(&load_const->def.uses))
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<
alyssa >
I guess strictly that should also have an `&& !nir_ssa_def_is_used_by_if(&load_const->def)`
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<
alyssa >
though it probably doesn't matter
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<
alyssa >
and also that's in an opt pass
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<
alyssa >
the other change to intel/compiler is completely mechanical so won't be the problem
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<
alyssa >
so.. either some issue in the NIR changes that somehow doesn't affect anything in CI, or preexisting bug or somthing
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<
HdkR >
Ah, DOTA underlords immediately hecks up this allocation. Got it, no one does memory allocations and freeing correctly.
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<
Kayden >
hm okay it's not a intel optimization issue, the code we generate after translating from NIR is now invalid
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<
Kayden >
but the NIR is identical...?
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<
alyssa >
Memory unsafety doom?
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<
Kayden >
I found it
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<
Kayden >
our ballot handling is reading instr->dest.ssa.bit_size
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<
Kayden >
the destination is a register
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<
Kayden >
hello garbage reads
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<
Kayden >
also hello unrelated pre-existing bug that just never got hit
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<
daniels >
dj-death: it’s definitely not normal, but it does happen sometimes and that’s actively being worked on
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<
kode54 >
my Arc card is showing Graphics Pipeline Library support
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<
kode54 >
but the build of Mesa I'm using doesn't have that MR merged
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<
kode54 >
disregard that
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<
kode54 >
vulkaninfo is showing properties of swrast too
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<
kode54 >
thanks again for pushing it closer to inclusion
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<
mareko >
tarceri: I wonder how much effort it would be to do UBO linking in NIR, i.e. gathering ubo variables from NIR rather than GLSL
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<
mareko >
does NIR have instruction-level dominance computation helpers?
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<
mareko >
I wouldn't like to reinvent the wheel, I'm mainly interested in instruction-level dominance and post-dominance
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<
mareko >
I'll probably start typing that after I'm finished with moving uniform blocks and UBO loads in shader outputs to the next shader stage
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<
mareko >
which mostly works
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<
mareko >
cwabbott: ^^
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<
cwabbott >
mareko: I think there's already instruction-level dominance but not post-dominance
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