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<kode54> wouldn't know the first thing to bisect to find what may be causing this
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<danvet> pq not here ...
<danvet> daniels, ^^ maybe
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<danvet> emersion, this makes me wonder, do we need to formalize kms uapi reviewers?
<danvet> it's a bit hard to catch with a MAINTAINERS entry because it's all over
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<emersion> ah, i've actually never used CTM
<emersion> JoshuaAshton: ^ does this match your experience?
<emersion> danvet, that would be nice. i think we already ask people to CC wayland-devel for new props?
<danvet> emersion, is that documented anywhere?
<danvet> I'm also wondering whether we could at least make some pattern matches in MAINTAINERS
<danvet> like matching the uapi header file is easy, but many props are just all over
<emersion> hm i thought so, but apparently not
<danvet> plus often the important stuff is in the kerneldoc and I don't think there's a way to match that
<danvet> emersion, I guess at least a "DRM KMS UAPI" MAINTAINERS entry that matches include/uapi/drm/drm_mode.h?
<danvet> as a start at least
<jannau> that ctm order is what Apple display processor FW expects and is used by kwin 5.27.3 and later
<emersion> maybe we can move the KMS prop docs to a rst
<emersion> hm, not sure that'd be a welcome change
<emersion> but yeah maybe start with drm_mode.h and we can improve later
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<javierm> danvet: why are you looking fbmem and fbcon again?
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<Lynne> how is it possible a memory load after 10s of barrier(); and memoryBarrier(); and everything else I could think of still differs between compute local invocations within a workgroup?
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<ishitatsuyuki> Lynne: IIUC, neither barrier nor memoryBarrier will flush caches unless the variable is marked as coherent
<ishitatsuyuki> hm, but you mentioned within a workgroup
<ishitatsuyuki> so, technically, barriers only ensures coherency for shared memory
<ishitatsuyuki> but as far as AMD hardware is concerned, memory access within the same workgroup should be coherent
<Lynne> I've tried both nvidia's binary drivers and radv, the behavior is the same
<Lynne> the only way I know I'm somewhat sane is that if I do another dispatch with a memory barrier, the memory looks fine
<Lynne> but I really want to do the processing in a single shader, since barriers completely kill performance
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<Lynne> adding coherent doesn't fix the issue either
<Lynne> I'm using BDAs if it matters
<Lynne> this is my shader if anyone's interested - https://paste.debian.net/1277097/
<Lynne> issue is at line 313
<Lynne> the same value should get splatted horizontally, but yet, after x = height[0], the old value is written instead, as if prefix_sum() wasn't even called
<Lynne> if I put a hardcoded value for a, it works, if I don't call prefix_sum() the second time it works
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<ishitatsuyuki> Lynne: if I understand correctly, the decoupled lookback algorithm only waits for indices up to the thread's job to complete before continuing. hence loading v[4096200] feels a bit suspicious to me, unless this is conditioned to only happen for the last workgroup
<Lynne> it's just a convenient index, since it's non-zero, it breaks with any index
<ishitatsuyuki> Are the prefix sums global? Are there sufficient synchronization before and after the prefix sum to ensure src/dst writes are visible?
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<Lynne> global?
<ishitatsuyuki> Are you doing prefix sums across workgroups?
<Lynne> no, there's only a single workgroup dispatch
<ishitatsuyuki> so vkCmdDispatch(1,1,1)?
<Lynne> yup
<ishitatsuyuki> weird
<Lynne> I can push the code somewhere with instructions to run it if you find it interesting enough
<ishitatsuyuki> looks like RDNA can actually have two L0 cache within a dual compute unit, where the same workgroup can be scheduled
<ishitatsuyuki> when you added coherent, where did you add it to?
<Lynne> in both the buffer definition (coherent buffer DataBuffer) and the pushConstants pointer
<ishitatsuyuki> I guess that should do the job
<ishitatsuyuki> busy with other stuff right now but I'll check later to see if we're emitting the correct instruction flags for this case (workgroup running on dual CU)
<ishitatsuyuki> can you try barrier with explicit memory scope on nvidia?
<Lynne> explicit memory scope?
<ishitatsuyuki> lemme lookup the syntax but it's from vulkan memory model
<ishitatsuyuki> controlBarrier(gl_ScopeWorkgroup, gl_ScopeWorkgroup,gl_StorageSemanticsBuffer,gl_SemanticsAcquireRelease)
<Lynne> same output on both radv and nvidia after putting it right after the barrier() call
<Lynne> same == wrong
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<ishitatsuyuki> I think you need it before and after the prefix sum too
<ishitatsuyuki> (for the src/dst synchronization I mentioned above)
<Lynne> hey, that did something!
<Lynne> still not correct, but it looks a bit more correct now
<HdkR> karolherbst: Congrats on rusticl for radeonsi merge! Next stop rusticl for Freedreno? :D
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<Lynne> hmm, it still looks as wrong in my regular use-case rather than this hacked-up simplified version
<danvet> narmstrong, so you'll apply the bridge maintainer patch with all the fixups?
<narmstrong> danvet: yup, or you can resend as you wish
<danvet> nah happy if you take care :-)
<narmstrong> danvet: sure!
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<javierm> danvet: I think narmstrong's suggestion was to fix the author field though
<javierm> while in the past you asked to add both S-o-B tags
<narmstrong> I can do either just tell me
<karolherbst> HdkR: probably just works.. or maybe not as it needs some func pointers, dunno...
<karolherbst> I don't have hardware :D
<narmstrong> danvet: ok to add both SoB then?
<danvet> sure
<mlankhorst> danvet: is the merge window for v6.4-rc1 still open?
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<danvet> mlankhorst, I guess one last -next pull or something
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<mlankhorst> sent, didn't look too spectacular. :)
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<HdkR> karolherbst: Sounds like a good reason to get such hardware :P
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<danvet> mlankhorst, did you prep drm-misc-next-fixes already?
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<mlankhorst> danvet: hm no, should that not be drm-next after merge?
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<danvet> mlankhorst, yup, and that's pushed now so you can forward
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<robclark> danvet: how to link to rst?
<danvet> note that functions should auto-link anywhere
<danvet> there's actually good docs for the kernel's doc system :-)
<robclark> so just use full path then
<danvet> well if you want a specific chapter in an .rst then it gets more tricky
<danvet> need to put a sphinx tag above the heading and reference that
<robclark> full path I think is better.. because it is also something that looks sensible to someone looking at code instead of html ;-)
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<robclark> `make htmldocs` does take some time..
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<danvet> robclark, incremental is a lot better
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<mlankhorst> done
<mlankhorst> drm-misc-next is closed!
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<javierm> danvet, jfalempe: any idea how my patch could had made things worse? That's very surprising... https://lists.freedesktop.org/archives/dri-devel/2023-April/399981.html
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<DavidHeidelberg[m]> robclark: a630 showing huge performance boost, any particular commit you suspect? :D https://gitlab.freedesktop.org/mesa/mesa/-/issues/7144#note_1865796
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<DavidHeidelberg[m]> gallo: performance go brrrrr ^ :)
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<robclark> more likely the latter
<robclark> there was also a kernel fix for anything doing short duration (<10ms) fence waits.. not sure if that shows up in any traces (stk does this)
<robclark> (hmm, well the kernel fix might actually make the trace appear slower since the trace is just a pre-recorded # of fence waits and nothing to do with reality)
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<karolherbst> dcbaker: seems like bindgen is doing incompatible changes and we have to know the version in meson :(
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<Lynne> ishitatsuyuki: any ideas on how to fix this?
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