<machinehum>
Is there any buildroot support for Lindenis_V5 ?
<machinehum>
The Allwinner V5 SoC
<machinehum>
Well the Lindenis_V5 is a board, but it has a Allwinner V5 on it
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<apritzel>
machinehum: there is no mainline support for the V5, neither for U-Boot nor Linux
<apritzel>
looks like one of those "modern" A7 SoCs, which use the SoC design (clock & memory map) of the H6
<machinehum>
Speaking as someone that's never done this before, what's the practicality of me merging their code from their "forks" into mainline and it working
<machinehum>
By merging I mean locally and not upstreaming... as upstreaming wouldn't be allowed?
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<wens>
apritzel: IIRC the delay in the SoC is not on the same scale as the 2ns delay used for RGMII; it's only for fine tuning
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<apritzel>
wens: yeah, I was wondering about that, of course the manuals don't mention any scale
<apritzel>
wens: the kernel's Micrel PHY driver has all the runes to create or suppress any delays there, so we should not need any MAC delay, for *that* purpose
<apritzel>
but it seems like many A20 boards use that MAC TX delay, even with a Realtek PHY and rgmii-id
<apritzel>
so that might indeed be something independent of the RGMII spec delay
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