05:09 <jernej> apritzel: no, just curious if we missed oportunity for increased perfomance by not specifying l2 cache in DT

12:01 <apritzel> jernej: recent cores integrate the L2 cache controller (and SCU) quite tightly, I think you cannot even disable the L2 apart from clearing SCTLR.C (thus disabling L1 as well) on a Cortex-A53

12:04 <apritzel> jernej: so: sorry, no low hanging performance fruit here ;-) Running without the L2 cache would have been quite dramatic anyway, we would have surely noticed that before

12:21 <mripard> jernej: iirc, only the Cortex-A9 has required an L2 cache controller described in the DT

16:53 <jernej> mripard, apritzel: here is specified for rk3328: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/rockchip/rk3328.dtsi#L103-L105

16:54 <jernej> which has cortex a53 cores, same as H6

16:54 <jakllsch> could just be cargo-culted

16:54 <jernej> so I thought we missed something, but thanks for explanation