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<
apritzel >
benettig: yes, mainline U-Boot won't work with FEL on the F1C100s, never did
00:26
<
benettig >
apritzel: I've used that u-boot repository, I haven't mentioned it because you've quitted, so I've written all this here:
00:26
<
benettig >
and unfortunately it doesn't work :-/
00:27
<
benettig >
apritzel: tbh I've tested it on a F1C200s board, not LicheePi
00:27
<
benettig >
I need to find the one with soldered pins to connect serial port
00:29
<
apritzel >
benettig: mmh, interesting, thanks for testing
00:29
<
benettig >
apritzel: wait I give a go with Lichee, I've found the second one with soldered pins
00:29
<
apritzel >
I don't think it's F1C200 related, from all I know it's the same, just with more DRAM
00:30
<
benettig >
apritzel: yeah, honestly I think it's the same, but I give a try
00:30
<
benettig >
apritzel: does it work for you instead? On LicheePI?
00:31
<
apritzel >
the combination of the two works for me, on the LicheePi
00:32
<
apritzel >
but I need both: the U-Boot patch (other F1C100 trees worked as well), plus the sunxi-fel patch (or use Icenowy's branch)
00:32
<
apritzel >
with Icenowy's sunxi-tools you still need the U-Boot patch
00:33
<
apritzel >
(when using mainline)
00:34
<
apritzel >
benettig: oh, and do you have an oscilloscope, and can measure the SPI clock frequency?
00:35
<
benettig >
So to recap. It works for you with:
00:35
<
benettig >
Correct?
00:35
<
benettig >
:-/ not here on F1C200s, but let me check with 100s
00:36
<
benettig >
I'm finding the pinout
00:36
<
benettig >
I've disconnected it
00:36
<
benettig >
and I do have a scope
00:36
<
benettig >
do you need to know the SPI frequency so, right?
00:38
<
benettig >
apritzel: can you point me where to find the Licheepi-nano schematics? They seem gone anywhere
00:39
<
benettig >
apritzel: nevermind, I've found it at the first search. I've passed like 2 hours 1 month ago and nothing.
00:39
<
benettig >
file:///home/giuliobenetti/Downloads/lichee_nano_8.16(Schematic).pdf
00:39
<
benettig >
thank you!
00:39
<
benettig >
don't know I couldn't find it 1 month ago
00:41
<
apritzel >
so yeah, the F1C100 doesn't have a SPI modclock, so it's probably tied to AHB
00:41
<
apritzel >
but it would be good to know that for sure
00:42
<
benettig >
apritzel: ok for SPI
00:42
<
benettig >
I check it
00:43
<
benettig >
apritzel: now when I try sunxi-fel uboot it runs 12 times SPL with:
00:44
<
benettig >
U-Boot SPL 2022.01-22959-g7073bf7509 (Mar 03 2022 - 22:07:50 +0100)
00:44
<
benettig >
DRAM: 32 MiB
00:44
<
benettig >
Trying to boot from FEL
00:44
<
benettig >
sudo ./sunxi-fel uboot ../build-uboot/u-boot-sunxi-with-spl.bin
00:44
<
benettig >
But in host I still have the problem of:
00:44
<
benettig >
usb_bulk_send() ERROR -7: Operation timed out
00:44
<
apritzel >
benettig: if you try with sunxi-fel spiflash-read, it should be 6.25 MHz
00:45
<
benettig >
apritzel: now I check spi-flash speed
00:45
<
benettig >
apritzel: but is it correct to have the timeout in sunxi-fel? I mean, is it meant to be that way or not? I'm not used to sunxi-fel that much honestly
00:45
<
apritzel >
benettig: no, it should return
00:46
<
benettig >
apritzel: ok, so there is still the problem
00:46
<
apritzel >
the U-Boot build hash suggests that's the version you mentioned above
00:46
<
apritzel >
that's
*not* the version ...
00:46
<
benettig >
apritzel: really?
00:47
<
benettig >
let me re-check
00:47
<
apritzel >
well, it's not sunxi/master
00:48
<
benettig >
apritzel: damn it, I've used f1c100s branch, that's why! Sorry
00:48
<
apritzel >
did you fetch/pull? that hash above was master until yesterday
00:48
<
benettig >
going to rebuild
00:50
<
benettig >
apritzel: yeah!! It works! Sorry for the false alarm!
00:50
<
benettig >
Now I check SPI flash clock
00:50
<
apritzel >
cool, thanks
00:54
<
benettig >
apritzel: 6.25Mhz confirmed!
00:55
<
benettig >
and that should also explain why I can read at 200Kb/s only
00:55
<
apritzel >
great, that means it's really the 200 MHz AHB being used as the clock source
00:55
<
apritzel >
benettig: well, sunxi-fel plays it safe, and uses 6 MHz, because that's what the BROM does as well, IIRC
00:56
<
apritzel >
it doesn't really know the board design or flash chip, so assumes the worst
00:57
<
benettig >
apritzel: ah yeah, it would be cool to tweak the prescaler to speed up the flash
00:57
<
apritzel >
benettig: well, you can do that in
*your* copy, if you like, but for mainline we prefer a safe value
00:58
<
benettig >
only 6Mhz?
00:58
<
benettig >
we should increase it with dts spi speed property
00:59
<
benettig >
is the driver in DT or legacy?
00:59
<
apritzel >
benettig: if you replace the CCM_SPI0_CLK_DIV_BY_32 with ..._BY_6, in sunxi-tools/fel-spiflash.c, it should go to 33.3 MHz
01:00
<
apritzel >
that's just the safe, hardcoded value to sunxi-tools
01:00
<
apritzel >
both U-Boot and Linux will use higher speeds
01:00
<
benettig >
I give a go using sunxi-fel itself to write on the address
01:00
<
apritzel >
U-Boot proper, that is, the SPL code also uses the slower rate
01:01
<
benettig >
to load the uboot to dram?
01:01
<
benettig >
ah but yes
01:01
<
benettig >
it's only some 2-300KB
01:01
<
benettig >
I'm only thinking in production
01:01
<
benettig >
for sunxi-fel
01:01
<
benettig >
maybe a parameter is worth to set the spi speed
01:02
<
benettig >
s/speed/frequency
01:02
<
apritzel >
well, I think this is limited by the FEL speed anyway
01:03
<
benettig >
there are a lot of holes between the readings
01:03
<
benettig >
really bigger than the reads themselves
01:06
<
benettig >
too much overhead
01:07
<
apritzel >
ah, indeed
01:08
<
apritzel >
(and I was eyeing that Rigol too, although the 2 channel version only ;-)
01:08
<
apritzel >
I don't get it beyond 256 Kb/s, as reported by sunxi-fel
01:09
<
benettig >
:-) it's more than good enough to do this stuff.
01:09
<
benettig >
so sunxi-fel has that 14mS overhead
01:09
<
benettig >
or fel itself
01:09
<
benettig >
it's crazy, USB at least should go @1.5Mbps
01:10
<
apritzel >
both, somewhat, the implementation uses only a small buffer, so can't collect more data in one go
01:10
<
benettig >
apritzel: ah that makes a lot of sense. It's only that it scares me a bit for production
01:11
<
benettig >
ah no wait
01:11
<
benettig >
I only ignite uboot+linux+ramdisk
01:11
<
benettig >
and that's it
01:11
<
benettig >
as I've done with A20
01:11
<
benettig >
and then Linux takes over and shows the eMMC or Nand as mass storage
01:11
<
benettig >
so no problem
01:12
<
benettig >
I correct the github issue and go to bed
01:12
<
benettig >
apritzel: thank you for improving sunxi-fel!
01:12
<
apritzel >
on the F1C100, the SPI buffer is only 4K, I might be playing around with making it bigger
01:12
<
apritzel >
and the FEL speed is limited by the OTG BROM implementation
01:13
<
benettig >
I think it's most of all the OTG BROM the problem
01:13
<
benettig >
the SPI buffer of 4K is pretty big. Flash should have 512 sectors(I think)
01:13
<
apritzel >
there are hints out there that you can switch to HighSpeed, with dramatic effects
01:13
<
benettig >
but on SPI side you mean?
01:14
<
benettig >
because the problem I see is the overhead of OTG BROM
01:14
<
benettig >
14mS(OTG BROM overhead) VS 3mS(the reading)
01:14
<
apritzel >
well, but if you need less round trips, because the buffer is bigger, the overall speed should increase
01:14
<
apritzel >
so that makes 17 ms per 4K
01:15
<
apritzel >
when you could read 8k, it would make 20ms per 8K
01:17
<
benettig >
yes the timing calculations says the same 4096 bytes
01:18
<
apritzel >
it's not trivial to increase the buffer size, though
01:19
<
benettig >
but, do you mean the buffer size created by sunxi-fel, right?
01:20
<
benettig >
because the SPI peripheral itself has 64 FIFO and that's it
01:20
<
benettig >
or they use DMA in some way
01:20
<
apritzel >
benettig: yes, sunxi-fel's buffer size, it's using the beginning of SRAM till the scratch address
01:21
<
benettig >
mmh, we have 40K total
01:21
<
benettig >
at least I see from Datasheet
01:21
<
apritzel >
yeah, but some of is used by the BROM FEL code
01:23
<
apritzel >
it uses two stacks just in the middle of the SRAM, making our life extra painful
01:23
<
benettig >
IRQ and FEL stacks
01:24
<
benettig >
so only 15K left for all
01:24
<
apritzel >
well, there if definitively more space, somewhere, it's just not trivial to find, and even harder in a upstreamable fashion
01:24
<
apritzel >
because the code needs to work for every SoC
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<
apritzel >
for production I would either boot of SD card, then use a U-Boot script and flash using U-Boot's sf command
01:26
<
apritzel >
or just load U-Boot, then use U-Boot's OTG code, for instance via fastboot
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<
apritzel >
but it's a bit more tricky to setup
01:26
<
benettig >
apritzel: yes, exactly
01:27
<
benettig >
it's like how I do now for all A20/A33 etc.
01:27
<
apritzel >
and from what I saw, I guess the auto-script feature of sunxi-fel wouldn't work
01:27
<
apritzel >
(on the F1C100, at the moment)
01:27
<
benettig >
oh, I'm very new to sunxi-fel so I've never tried it out
01:28
<
benettig >
anyway I think this is already a very good result
01:28
<
apritzel >
basically you can upload a U-Boot script, and U-Boot would
*automatically* execute that
01:28
<
benettig >
if increasing speed could lead to double the throughput, so let's say 400-450KB/s
01:28
<
benettig >
apritzel: yes exactly what I do
01:29
<
benettig >
that in the end is the same stuff i.MX stuff does
01:29
<
benettig >
same goes for TI
01:29
<
benettig >
and so on
01:29
<
benettig >
i.MX6 uses mfgtools that loads uboot+linux and communicate
01:29
<
benettig >
but for my needs it's easier u-boot+ums and that's it
01:30
<
benettig >
apritzel: well, need to go to bed
01:30
<
benettig >
apritzel: it's been a pleasure :-) Ping me if you need some help. I try to arrange with all other activities
01:31
<
apritzel >
alright, have a good rest
01:32
<
benettig >
Thank you, talk soon
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19:32
<
anarsoul >
I think it's only for their newer GPUs
19:41
<
jernej >
sure, but few days ago was talk about new AW SoC with new PowerVR GPU
19:45
<
jernej >
although, looking at that now, I'm not sure which PowerVR GPU should be present
19:46
<
jernej >
gamiee: which soc did you have in mind when talking about PowerVR GPU?
19:48
<
gamiee >
jernej: hi, I meant A133
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<
ndufresne >
MT8173 isn't exactly "new", so that probably includes quite some HW, seems like a good news for sure
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