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<smaeul> machinehum: are you looking for pin function/mux information or the mapping to BGA?
<palmer> does anyone have a link to ISA manual for the T-Head C906 / Allwinner D1? I remember seeing one, but can't find it any more
<smaeul> the port controller section of the V5 manual (11.8.5) has the functions for each pin, and any board schematic (e.g. http://files.lindeni.org/lindenis-v5/datasheets/lindenis-v5-schematic-v1.1.pdf) will have the ball listed next to each pin
<palmer> smaeul: IIRC there's an English one somewhere?
<palmer> ya, that's it -- thanks!
<smaeul> the english one is not complete. it just has instructions, not the extra CSRs
<palmer> that's OK, I think we just need the cache instructions for now
<palmer> IIRC I asked for the CSR bits in an issue, but I guess nothing changed
<palmer> one step at a time, though ;)
<smaeul> also there are enough copy/paste errors in the english one that I trust a translation of the Chinese one more
<palmer> ;)
<palmer> I've only skimmed it, so I guess I'm in for a trip
<machinehum> smaeul: Ideally I want something like the normal allwinner datasheets, which tells me which pins have which alternate function etc
<machinehum> Also what you said
<smaeul> yeah, all of that information is in the user manual in the PIO register descriptions. it's just not as neatly formatted
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<machinehum> smaeul: Thanks I'll take a look
<machinehum> It's looking like several memory locations are different between the V5 and H6
<machinehum> So I will have to remove SUN50I_GEN_H6 as that includes the H6 memory map, and write my own
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