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MoeIcenowy>
smaeul: for SPI timing, did you read a section about SPI sampling in R329 user manual?
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MoeIcenowy>
(I sent this via mail, but aosc.io mail service now has ridiculous rate limit and the mail got limited
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MoeIcenowy>
okay D1 user manual has this section too
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MoeIcenowy>
it says for <=24MHz normal clock, 24~40 delay half cycle, 80+ delay one cycle
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smaeul>
MoeIcenowy: yes, but I'm not sure what to make of it
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smaeul>
I suppose I need to get out a logic analyzer to see what the timing is like with the default ("old mode") delays
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MoeIcenowy>
how much freq did you use to read spi nand
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MoeIcenowy>
well I have a LA, but out of quarantine, and my quarantine will only end at 29th
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MoeIcenowy>
well maybe LA can solve nothing because this defines how the chip samples
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MoeIcenowy>
not how the chip outputs
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smaeul>
right now I have 100 MHz working with the new mode. I don't remember what all frequencies I tried with the old mode, that was last July
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smaeul>
it was definitely much lower. IIRC I tried multiple frequencies in each of the ranges given in table 7-13
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MoeIcenowy>
reading r329 bsp now
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MoeIcenowy>
in sunxi_spi_xfer_setup
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MoeIcenowy>
there seems to be code that sets sample delay, calling spi_sample_delay()
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MoeIcenowy>
for >=60M it sets SDM=0, SDC=1
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MoeIcenowy>
for <=24M SDM=1 SDC=0
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MoeIcenowy>
otherwise both 0
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MoeIcenowy>
well it's weird that the BSP does not touch BIT(2) of 0x04
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MoeIcenowy>
only touching SDM and SDC
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