00:11 <machinehum> I've been using a uboot patch with buildroot and using the sdcard.img, but I'll start flashing the u-boot-sunxi-with-spl.bin directly

00:13 <apritzel> yeah, I'd prefer removing all those middle men, too many things that could go wrong, especially with a new SoC

00:36 <apritzel> machinehum: get https://paste.c-net.org/ShavedDumber, and write that to the SD card (as above)

00:39 <machinehum> dd it?

00:39 <machinehum> Or copy the file

00:39 <machinehum> Also

00:40 <machinehum> What about all the AXP805 stuff?

00:40 <machinehum> Should that not all be enabled in uboot, set the regulator voltages, etc...?

00:53 <apritzel> machinehum: you should try walking before you run ;-)

00:54 <apritzel> machinehum: dd if=uart_init_v5.sunxi of=/dev/sdX bs=1k seek=8

00:54 <apritzel> (where /dev/sdX is the name of your SD card block device)

00:54 <apritzel> for now we just need the SPL to print the banner, there is no AXP needed at this point

00:55 <machinehum> apritzel: GOtcha

00:55 <apritzel> and the DRAM controller might be the biggest hurdle anyway

00:57 <machinehum> HELLLOOOO!

00:57 <machinehum> https://pastebin.com/raw/iWT96Fkf

00:57 <machinehum> That's exciting

00:58 <apritzel> very good! This also puts the board in FEL mode (in case there is no FEL button)

01:24 <machinehum> Do you have a diff for that? What is going on here

01:26 <apritzel> machinehum: this is just some pure assembly to initialise the UART according to the V5 manual and output something, wrapped in an eGON image

01:28 <apritzel> it just proves that the UART works with those parameters

01:29 <apritzel> try to write spl/sunxi-spl.bin in the same way, with your branch or my patch plus the proper UART pinmux setup, and see if that works

02:20 <machinehum> No dice on that

02:26 <machinehum> Where do these numbers come from? https://github.com/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-sunxi/cpu.h#L17

02:29 <machinehum> OH

02:29 <machinehum> Does SUNXI_DRAM_DW need to be enabled?

02:37 <machinehum> Nevermind

02:50 <machinehum> SUNXI_DRAM_CTL0_BASE Seems to be different between the H6 and V5

04:14 <jernej> DRAM is initialized after UART, so you should worry about that after you get something printed on UART

13:54 <MoeIcenowy> machinehum: are you trying to mainline V5 u-boot?

15:01 <apritzel> MoeIcenowy: yes, he does, but it doesn't work yet, so mainlining comes much later, I guess

15:01 <apritzel> MoeIcenowy: do you have patches lying around, by any chance?

17:06 <machinehum> MoeIcenowy: Yes

17:06 <machinehum> Been trying for the past 2 weeks or so

17:06 <machinehum> jernej: Alright

17:10 <machinehum> MoeIcenowy: RE patches, that would be relly helpful

22:09 <pentabarf1> Hi, one year ago @smaeul gave me a hint how to verify the rotpk by using a challenge-response mechanism in the SID. I didn't get it to work then. Now i am trying again. smaeul said "write the ROTPK to SID+0x120...SID+0x140, then set bit 31 of SID+0x140. wait 256 cycles and check SID+0x140 again. I believe bit 1 set means ROTPK is nonzero, and bit 0 means it matches what you wrote". He also said it is for H616 NBROM and i am

22:09 <pentabarf1> his is my code so far: https://gist.github.com/pentabarf/8695459ce25b289ae068fd6091502c9c But it is not working right now. What am i missing?

23:29 <apritzel> pentabarf1: does this actually work from the non-secure side, in Linux?