<apritzel>
very good! This also puts the board in FEL mode (in case there is no FEL button)
<machinehum>
Do you have a diff for that? What is going on here
<apritzel>
machinehum: this is just some pure assembly to initialise the UART according to the V5 manual and output something, wrapped in an eGON image
<apritzel>
it just proves that the UART works with those parameters
<apritzel>
try to write spl/sunxi-spl.bin in the same way, with your branch or my patch plus the proper UART pinmux setup, and see if that works
<machinehum>
Does SUNXI_DRAM_DW need to be enabled?
<machinehum>
Nevermind
<machinehum>
SUNXI_DRAM_CTL0_BASE Seems to be different between the H6 and V5
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<jernej>
DRAM is initialized after UART, so you should worry about that after you get something printed on UART
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<MoeIcenowy>
machinehum: are you trying to mainline V5 u-boot?
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<apritzel>
MoeIcenowy: yes, he does, but it doesn't work yet, so mainlining comes much later, I guess
<apritzel>
MoeIcenowy: do you have patches lying around, by any chance?
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<machinehum>
MoeIcenowy: Yes
<machinehum>
Been trying for the past 2 weeks or so
<machinehum>
jernej: Alright
<machinehum>
MoeIcenowy: RE patches, that would be relly helpful
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<pentabarf1>
Hi, one year ago @smaeul gave me a hint how to verify the rotpk by using a challenge-response mechanism in the SID. I didn't get it to work then. Now i am trying again. smaeul said "write the ROTPK to SID+0x120...SID+0x140, then set bit 31 of SID+0x140. wait 256 cycles and check SID+0x140 again. I believe bit 1 set means ROTPK is nonzero, and bit 0 means it matches what you wrote". He also said it is for H616 NBROM and i am