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<smaeul> A50 has the same hybrid configuration as V5, with the old DRAM controller but the new MBUS. (reference A64-BSP-4.0/bootloader/uboot_2014_sunxi_spl/sunxi_spl/dram/sun8iw15p1/dram/lib-dram/mctl_hal.c)
<smaeul> (unless of course you don't want to look at that file for legal reasons)
<smaeul> MoeIcenowy: yes, that is new. I suppose that was done to save mask ROM space, although it probably makes bugs more likely. I only have two D1 boards, so I have not been brave enough to blow a fuse yet.
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<MoeIcenowy> smaeul: any available mctl-hal.c could be leftover of unfinished development code
<MoeIcenowy> and not promised to work
<MoeIcenowy> but what is A50? I get out of date...
<MoeIcenowy> apritzel, smaeul: my R329 code could be reference for new com + old ctl
<MoeIcenowy> V831 is this too (in fact my R329 code is based on my local code for V831, but I didn't continue on V831 because of weird policy on its NPU
<smaeul> A50 (sun8iw15p1) is a quad-A7 tablet SoC
<smaeul> MoeIcenowy: can V831 and R329 share a DRAM driver?
<smaeul> I have the Sipeed V831 board, which would be nice to have working eventually
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<MoeIcenowy> smaeul: well yes
<MoeIcenowy> if you wonder I will send out my orig driver code
<smaeul> sure, that would be helpful
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<MoeIcenowy> smaeul: well I found that it's already on my gh
<MoeIcenowy> maybe I pushed it when I was transferring it to Sipeed ;-) (I finished my R329 code as part of Sipeed internship
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<apritzel> smaeul: MoeIcenowy: many thanks, very good hints!
<apritzel> smaeul: when you say "old DRAM controller but the new MBUS", this means just the priority settings are like the H6, but the other mctl_com registers are still like in the H3/A64?
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