#linux-sunxi on 2022-06-22 — irc logs at oftc.irclog.whitequark.org

2022-03-22 11:56 ChanServ changed the topic of #linux-sunxi to: Allwinner/sunxi development - Did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait for an answer! - This channel is logged at https://oftc.irclog.whitequark.org/linux-sunxi

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00:41 <machinehum> aperezdc_: Thanks for those values

00:42 <machinehum> I'm still a little lost on this guy https://pastebin.com/raw/RWYAmrBQ so smaeul you're saying that my disassembly of boot0 will not contain these values?

00:42 <machinehum> I guess is the boot0 loaded right at 00020000h? Because if so it looks like para is the contents at 0x38 which I've listed

00:44 <apritzel> machinehum: yes, AW uses a struct with the DRAM values, and places it near the beginning of the boot0 binary

00:45 <apritzel> they would appear in a boot0 disassembly, but not in libdram disassembly

00:46 <machinehum> To be clear I'm talking about the "para" argument of init_DRAM, not the values you sent to me

00:46 <apritzel> I understand

00:46 <machinehum> Okay

00:46 <apritzel> I don't remember right now what the first 8 is, but 792 is the frequency (in MHz), and 7 is the DRAM type

00:46 <apritzel> IIRC 7 is LPDDR3

00:47 <apritzel> those are the easy things, the more interesting specific timing values come next, mostly encoded already to be written directly into registers

00:48 <machinehum> So https://pastebin.com/raw/K0xzEauv

00:48 <machinehum> So I can assume the values at 0x38 in boot0 are the struct values?

00:49 <apritzel> yes, most likely

00:49 <apritzel> where do those names come from? libdram?

00:50 <apritzel> ZQ looks definitely like a match, my boot0 says 003b3bfb, which is a typical value

00:50 <machinehum> I got the names from libdram yeah

00:51 <machinehum> Filled out the struct in boot0, because ghidra obviously didn't know what they were

00:51 <machinehum> The names that is

00:51 <apritzel> yeah, that part requires clever combining of the two

00:52 <apritzel> the rest looks matching as well, 0x1c70 looks like a valid MR0

00:53 <machinehum> My boot0 does not agree https://pastebin.com/raw/wYMZ3cfm

00:54 <machinehum> Unless I'm reading this wrong

00:55 <apritzel> looks alright to me ...

00:55 <apritzel> @0x38 is the frequency, and the rest follows

00:56 <apritzel> type, ZQ, ODT enable, ...

00:56 <machinehum> zq starts at 0x40 which is fb3b3b00

00:56 <machinehum> Oh

00:56 <apritzel> little endian

00:56 <machinehum> Endianess

00:57 <machinehum> Derp

00:57 <machinehum> I haven't done stuff like this since school, which was a while ago

00:58 <machinehum> Okay neat, so I can start working that into the code as well

01:04 <machinehum> Some of those MBUS_PORT_* are not in the enum, should I just add them?

01:05 <smaeul> apritzel: https://lore.kernel.org/linux-riscv/20220616115342.GA11289@lst.de/ -> https://www.spinics.net/lists/devicetree-spec/msg01053.html

01:10 <apritzel> smaeul: that is all very sad ...

01:12 <apritzel> machinehum: keep in mind that the MBUS_PORT values come from the H6 definitions, not from the A64 ones

01:14 <machinehum> So I'll have to use sunxi_mctl_com_reg etc from the dram_sun50i_h6.h

01:16 <smaeul> apritzel: why sad?

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01:45 <machinehum> apritzel where exactly did you get the PORT12, 27, etc... from? There not defined in dram_sun50i_h6.c

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11:35 <montjoie> smaeul: thanks, it works better. did uboot/sbi/etc does a dtb address change ? i needed to change dtb address in my CI

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12:13 <szemzoa> I'm porting the D1_spl bootloader to T113-S3, mcrl_hal.c and the others are working, but I got some errors after loading OP-TEE. Anybody has an idea what I missed here? https://pastebin.com/UBevgnF6

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22:30 <apritzel> machinehum: I decoded the ports back from dumping the registers after boot0 initialised the DRAM

22:31 <apritzel> a lot of them were 0 (hence the gaps), but those listed were programmed

22:32 <apritzel> I don't know that they stand for, but that doesn't really matter, as we just set them to the same values as boot0 does and are good

22:34 <apritzel> smaeul: sad because of both the RISC-V foundation not foreseeing the problem, and also AW (and friends) for ignoring the coherency requirement of the architecture

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23:31 <karlp> oh, that's gross. :(