<smaeul>
szemzoa: where did optee come from? did you build it yourself?
<smaeul>
if it is a vendor blob, it probably requires patching in some "head" structure at the beginning
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<szemzoa>
smaeul: I'm new in the magical world of the aw blobs, but I'm pretty sure the problem comes from some header tricks. I've a vendor based buildroot bsp, it generates an sdcard.img. Than I replaced the boot0 binary on the sdcard, and that is the output.
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<apritzel>
szemzoa: please don't get used to AW blobs, that is mostly a dead end, and a distraction from the real thing (mainline U-Boot)
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<szemzoa>
apritzel: ok, so for now, I'm finished with this spl, should I send it somewhere?
<apritzel>
szemzoa: we don't want this separate SPL, that's just a kludge for the D1, because that is RISC-V, not ARM
<apritzel>
szemzoa: what we want is to integrate the T113 into mainline U-Boot, which is not really complicated, if we ignore the DRAM part
<apritzel>
szemzoa: so if you could put what you have somewhere, I would, at some point, make a proper U-Boot port
<apritzel>
szemzoa: or you beat me to it ...
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<szemzoa>
apritzel: ok, understood. I don't touched u-boot in the recent years, so we will see how it goes :)
<apritzel>
szemzoa: yeah, don't sweat it ;-)
<apritzel>
for a start, a LOT has changed in U-Boot in the last years, and the sunxi port is special in some ways anyway
<apritzel>
but also I have some V5 patches in the making, which will probably cover the vast majority of the T113 port already
<apritzel>
so ideally it's the DRAM code, and then just announcing that the T113 is yet another ARMv7 SUN50I_GEN_H6 port with small DRAM
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<szemzoa>
apritzel: these are good news :)
<apritzel>
szemzoa: what is the hardware you are doing this on? some available devboard?
<apritzel>
so is the T113 the R528 with embedded DRAM? And the F133-A is the embedded DRAM version of the D1? And they are the same die, with the Cortex cores disabled in the RISC-V version?
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<szemzoa>
apritzel: I think yes. For example the D1 and T113 clock are the same, the difference is CPUX_AXI_CFG_REG on D1 is CCM_BASE + 0xD00, on T113 it's CCM_BASE + 0x500
<apritzel>
that's an annoying difference, but fits perfectly in what AW would do ;-)
<szemzoa>
apritzel: yes, took about an hour to figure out why the clock setup isn't working :)
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<smaeul>
apritzel: szemzoa: none of the registers moved between T113 and D1. the ARM clock is at 0x500 and the RISC-V clock is at 0xD00 on both. you just need to choose the right clock for the CPU you are running on
<apritzel>
smaeul: yeah, was wondering about that
<apritzel>
szemzoa: unfortunately "cheap board" is really relative these days, I find it for 32 USD on Aliexpress ...
<apritzel>
szemzoa: unless you have a cheaper source