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<smaeul> usually they are taken from the BSP boot0, either from the code or by dumping the registers afterward
<smaeul> you can get the list of ports from the BSP's Linux MBUS driver
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<machinehum> Thanks
<tuxd3v> hello guys
<tuxd3v> I am asking if somebody knows about a sbc that has BT5.0/5.1 support, and good support in general...ho and also cheap :?
<machinehum> I'm trying to analyse the boot0 code, namely I want to find the value of para during the init_DRAM(para) function call
<machinehum> Here's where I'm at: https://pastebin.com/raw/RWYAmrBQ
<smaeul> yeah, the DRAM parameters are in the boot0 header
<machinehum> I don't know why or how para points to 0x38, which is SRAM_BASE - 00020038h
<machinehum> If I can find those values I'm hoping I can then implement the DRAM code for the V5
<smaeul> no, it points to 00020038h, or 0x38 bytes into the boot0 binary
<smaeul> the start of the binary is a big header, including the eGON header. for example (different SoC, same build system): https://github.com/smaeul/sun20i_d1_spl/blob/mainline/nboot/main/boot0_head.c
<machinehum> Doesn't boot0 get dumped in SRAM?
<smaeul> yes, and SRAM A1 starts at 0x20000
<machinehum> Thanks for the into, jumping out now but I'll study it when I get home
<machinehum> info*
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<MoeIcenowy> smaeul: I tried to RE D1 BROM yesterday (to dig out how Allwinner BROM handles SPI NAND)
<MoeIcenowy> and found that the same BROM now handles both eGON.BT0 and TOC0.GLH
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<apritzel> machinehum: yeah, those priority values are only in the boot0 binary, not libdram. But there are more easily dumped from the regs after boot0 init'ed the DRAM
<apritzel> I can do this later tonight when I am back at the board
<apritzel> I am a bit doubtful that this will fix things, though, as I'd think that those values are just for fine tuning, and are not critical to the core operation?
<apritzel> machinehum: anyway, many thanks for your work on this, getting the SPL and DRAM init to work would simplify so much for upstreaming
<apritzel> machinehum: as mentioned, I got U-Boot proper to work, with MMC, and have some lead over why Ethernet doesn't work
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<machinehum> aperezdc_: I also doubt those values are the exact thing we need, but if they're simple to dump out that would be amazing
<machinehum> I can even do it, if you let me know how
<tuxd3v> any sbc with BT5.0/5.1 support around??
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<karlp> what parts of 5.0 do you need particuarly?
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<apritzel> machinehum: do you see accesses to 0x4002010 .. 0x400208c in the V5 libdram/boot0? probably a loop just writing stored values into every register in that range?
<apritzel> translating back the values I read doesn't make too much sense, so I am wondering if I am looking at the right range ...
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<machinehum> I can't find anything
<machinehum> I did a search in Ghidra, nothing
<apritzel> I see the "399" at mctl_com->tmr, as in the beginning of mctl_set_master_priority_a64()
<apritzel> but the rest doesn't really add up, unless I am holding it wrong
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<apritzel> ... and I do, because that's using the H6 sunxi_mctl_com_reg layout, of course
<apritzel> reading the values this way gives reasonable values, now just need to decode
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<apritzel> but that also means that at least mctl_com is the H6 type, not the A64 (sunxi_dw) version
<apritzel> machinehum: this is what I decoded, after the boot0 setup: https://pastebin.com/bhaiEPDb
<apritzel> that should correspond to writes at 0x4002210 .. 0x4002444