<jernej>
apritzel, smaeul: are you aware why 32 bit reads with devmem2 don't work anymore on H6, unless they are aligned to 8 bytes?
<jernej>
did something change in Linux 6.0?
<smaeul>
jernej: are you sure you are not using some version of devmem2 that uses "long" for "word" accesses?
<jernej>
hm... good point
<jernej>
I'm using whatever arch provides
<jernej>
let me self compile
<apritzel>
I thought that devmem2 was always broken in that respect?
<jernej>
it worked before, now I get "Bus error (core dumped)"
<jernej>
smaeul: thanks, that was it. I changed unsigned long to unsigned int in source and it works
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<apritzel>
jernej: but that was a problem already when the A64 appeared, so whenever you compile the userland tool for an LP64 system. So how did it work before?
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<jernej>
not sure, as I said, I used devmem from arch repo
<jernej>
but it's possible it was devmem (earlier version)
<apritzel>
I tried to fix it back then, but couldn't find a canonical source to report it to, and there were more problems
<apritzel>
smaeul: palmer: I think you settled this already, but just for the records: I don't think the R528 deserves a separate clock compatible
<apritzel>
because CLK_IS_CRITICAL is a Linux implementation details, and nothing that should be different in the DT
<jernej>
apritzel: I found and fix several small bugs in your AC200 driver, but that reveal 1 major and 1 minor issue
<jernej>
major: mdio driver for some reason doesn't deassert reset and enable clock
<jernej>
apritzel: I use "regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 3);" hack in ephy syscon driver to make it work
<apritzel>
in probe?
<jernej>
yes
<jernej>
oh, that 24 MHz clock selection can be considered as hack, too
<jernej>
it seems it can work with 27 MHz too
<apritzel>
mmh, that's odd, because I am pretty sure I saw the callbacks being called correctly, but then ran into some Linux clock framework problem
<jernej>
yes, because of extra ampersand :)
<jernej>
at least that was the source of kasan complaints
<apritzel>
and 27 Mhz is somewhat theoretical, at least in the actual implementations? But I mean we can query the parent frequency, and set the bit accordingly
<jernej>
it's possible when AC200 is used as standalone IC
<apritzel>
yeah, but that's what I mean with theoretical, because even then you probably use a 24 MHz clock
<apritzel>
but yeah, your fixed look legit, many thanks for digging into this
<jernej>
np :)
<apritzel>
I won't be near hardware till the end of the week, so can only check on the remaining problems then
<jernej>
btw, I get message: mdio_bus stmmac-0:01: Resources present before probing
<jernej>
and probing code seems to bail out with -EBUSY
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<jernej>
so maybe that's the reason it doesn't enable clock
<apritzel>
never saw this message before
<jernej>
apritzel: I have to correct myself. Reset is deasserted, just clock is not enabled
<jernej>
apritzel: reset handling is actually done with two functions, second is effectively just rename of the first, so mdio_device_reset() and phy_device_reset()
<jernej>
and second one is called in a lot of places
<jernej>
so I guess we have to rethink this part
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<jernej>
apritzel: so missing call is in phy_device_register(). I put clock enable call there too and now it works without ephy syscon driver hacks
<jernej>
mystery solved, now I can go to sleep :)
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