#linux-sunxi on 2022-09-12 — irc logs at oftc.irclog.whitequark.org

2022-08-14 19:44 ChanServ changed the topic of #linux-sunxi to: Allwinner/sunxi development - Did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait for an answer! - This channel is logged at https://oftc.irclog.whitequark.org/linux-sunxi

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11:58 <DasChaos> Hi folks,

11:58 <DasChaos> I'm working with the f1c100s for a while now. And had problems to get the SPI-NAND working. I got it working and wanted to share my results with you:

11:58 <DasChaos> 2) The SPL Loader needs to be in a special sunxi format. For that I found an bash script (https://github.com/bamkrs/openwrt/blob/dolphinpi-spinand/target/linux/sunxi/image/gen_sunxi_spinand_onlyboot_img.sh#L61)

11:58 <DasChaos> 1) It isn't implemented in mainline u-boot, i found a patch for v2020.07.11 (https://github.com/aodzip/buildroot-tiny200/blob/master/board/allwinner/suniv-f1c100s/patch/u-boot/0001-v2020.07.11.patch), this is the line in u-boot where spi-nand isn't yet implemented: https://github.com/u-boot/u-boot/blob/7e0edcadb09d55d5319fdc862041fd1b874476f5/arch/arm/mach-sunxi/board.c#L212

11:58 <DasChaos> I had a mail conversation with @apritzel about it, so he is probably interested.

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12:32 <apritzel> DasChaos[m]: thanks for sharing! Now we would still need someone who brings that in a proper mainline-able form ...

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12:52 <DasChaos> I saidly don't have the experience yet, to achieve such a thing.

12:54 <mripard> None of us had any experience when we started :)

12:57 <DasChaos> Did someone already work with i2c in u-boot with 1F1C00s?

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13:17 <apritzel> i2c on Allwinner in general works mostly out of the box, did you run into any problems

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13:32 <DasChaos> ```

13:32 <DasChaos> Yeah I'm getting a timeout in u-boot. I've added this to the device tree:

13:32 <DasChaos> compatible = "allwinner,sun6i-a31-i2c";

13:32 <DasChaos> i2c0: i2c@1C27000 {

13:32 <DasChaos> reg = <0x01C27000 0x400>;

13:32 <DasChaos> interrupts = <7>;

13:32 <DasChaos> clocks = <&ccu CLK_BUS_I2C0>;

13:32 <DasChaos> resets = <&ccu RST_BUS_I2C0>;

13:32 <DasChaos> pinctrl-names = "default";

13:32 <DasChaos> pinctrl-0 = <&i2c0_pins>;

13:32 <DasChaos> status = "okay";

13:32 <DasChaos> #size-cells = <0>;

13:32 <DasChaos> #address-cells = <1>;

13:32 <DasChaos> ```

13:32 <DasChaos> };

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14:43 <DasChaos> I hope my matrix -> irc connection is working now :)

14:43 <jakllsch> seems like it

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14:50 <apritzel> DasChaos: it works - although you should not paste large blocks into channels, but use some pastebin for that

14:53 <DasChaos> apritzel: Yeah, i thought it will be formated, will use it next time.

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14:55 <apritzel> Indeed I have seen some bridges automatically creating links for larger blocks before

14:55 <apritzel> DasChaos: does that node work in Linux? I had some mixed experiences with the IRC command in U-Boot

14:56 <DasChaos> apritzel: Yes that device tree node is working on Linux

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22:01 <cyrozap> apritzel: Out of curiosity, did you ever discover the root cause of the issue we discussed a few months ago, where the H616 U-Boot SPL would fail to return to FEL mode?

22:35 <apritzel> cyrozap: no, unfortunately not. I have a crude hack that seems to fix this (udelay(0); at some point), but I am reluctant to apply this as a fix

22:37 <apritzel> cyrozap: my gut feeling is that something is wrong with our MMIO accesses in general, I think some MMC related issues appearing lately also point in that direction

22:37 <cyrozap> Oof, yeah, I can totally understand not wanting to apply a hack without actually knowing _why_ it works, since it could break at any time or otherwise just be unreliable.

22:38 <apritzel> U-Boot's clrsetbits() routines lack any barriers, but I not convinced that would cause the issue

22:39 <apritzel> (because of how memory ordering works architecturally in this case and the comparatively tame hardware optimisation of a Cortex-A53 in particular)

22:41 <cyrozap> Could MMIO accesses be getting cached or something? I know caches are usually disabled by default, and when they are enabled MMIO address ranges are generally never cached, but with el-cheapo SoCs like these, maybe the designers messed something up?

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22:49 <apritzel> no, this would cause much more problems, and not even Allwinner can screw this up ;-)

22:50 <apritzel> however there are memory ordering rules to be observed, even with "device" memory attributes

22:53 <apritzel> but this typically only is problematic with more advanced cores, the RPi4 (Cortex-A72, so a "big" core) for instance has some reputation to reveal such problems

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22:59 <apritzel> another possibility would be that in general we miss some delays in the DRAM init procedure, and we just got lucky so far

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23:24 <smaeul> DasChaos: in arch/arm/include/asm/arch-sunxi/i2c.h set CONFIG_SYS_TCLK to 100000000

23:25 <smaeul> this is similar to the condition for CONFIG_SYS_NS16550_CLK in include/configs/sunxi-common.h (and we should move CONFIG_SYS_TCLK there, too)

23:25 <smaeul> you can also check that the clock/reset/pinctrl bits were applied correctly