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<stoniejohnson>
hi
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<marcan>
j`ey: two bits to enable isn't that odd, one might enable the peripheral as a whole or be a clock enable and the other actually enable the output
<marcan>
try slowing it down and toggling them individually - if you get it stuck on at some point, that bit is a clock enable
<marcan>
or if one of them kills the output mid-cycle and the other always waits for the end of a cycle, one is a hard/global enable (or reset?) and the other a softer enable
<marcan>
kettenis: probably a good idea for you to keep the u-boot DTSes up to date with an eye on BSD usage too, so then if you package that up you don't have to worry about me accidentally breaking you
<marcan>
(since we ended up using the linux ones in the distro, mostly to keep it synced with the kernel)
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<sven>
alright, looks like Bluetooth suspend/resume works fine on m1 if I write 0 to the sleep control register instead of 2
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<sven>
that register still bugs me. 0/1/2 doesn’t seem to make any difference except when resuming
<sven>
and macOS writing to it also doesn’t make much sense
<j`ey>
are you talking about #define BCM4377_BAR0_SLEEP_CONTROL 0x150 ?
<sven>
yes
<sven>
macOS seems to flip it between 0 and 1 on every interrupt and set it to 2 before it enqueues a command
<sven>
on m1/2 you can just not do that and everything works
<maz>
could that be some sort of mutual exclusion signalling between the two ends?
<sven>
on t2 you need to write 2 before each command because it’ll otherwise just not reply if it’s been idle for a second or so
<NikolayNikolaev[m]>
Offtopic, is there a link describing how to monitir these writes in Darwin?
<sven>
hm, not sure what it would protect. the register is called sleep control inside debug strings fwiw
<maz>
maybe that's to prevent opportunistic sleep on the BT end. flip it to 1 to make sure it is alive, and 2 forces a sleep?
<maz>
idle speculation...
<sven>
it actually flips it, as in write 0 if it was 1 and write 1 if it was 0
<sven>
I’m just guessing as well, speculation is very welcome :)
<maz>
the flip is really odd. it must be some sort of state change acknowledgement, but there are way simpler ways to do that...
<dottedmag>
NikolayNikolaev[m]: m1n1 has tracers, see the wiki
<sven>
yeah… and the commands are just queues and sending is update the head and ring a doorbell
<sven>
it’s very odd that it needs another kind of state change ack
<sven>
but then again, this is Broadcom and they have a “virtual transmission queue” that’s used to received data in the “completion queue”….
<maz>
but also, why mix this with sleep control?
<maz>
it looks totally unrelated.
<sven>
yeah
<sven>
but the 0/1 flip is one of the first things the interrupt handlers seems to do
<sven>
and the write 2 always happens just before they submit a command. it's very strange
<sven>
i should probably load the symbols and look at the backtrace whenever a write to that register happens just to rule out that this is a coincidence
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<povik>
marcan: please pull bits-update/000-devicetree and bits-update/070-audio
<povik>
it has the ADMAC driver as it is now in Linus's tree
<povik>
and the matching DT changes
<povik>
and some other DT fixes on top of it (audio related)
<povik>
(i would post fixups for the DT instead of a replacement branch, but i somehow managed having two identically named commits in the deviceetree branch)
<povik>
(^ that i fixed too)
<povik>
kettenis: i did it!
<kettenis>
thanks
<kettenis>
some coordination is still required I think, since if there is a mismatch between device tree and kernel, people will lose their audio
<povik>
well it was overdue...
<povik>
yeah
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<jannau>
marcan: fyi ceph's threadpool looks badly broken on my m1 mini install (gentoo's ceph 17.2.3 compiled with "-O2 -march=armv8.4-a")
<jannau>
abmysal revocery rates for replicated pools (5 - 15 MB/s) with high CPU load
<jannau>
perf top accounts 20% to pthread_mutex_lock and 10% to clock_gettime (+10% unknown symbol in vdso)
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