ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<sid-linux>
An aarch64 conceptual question. System register, say, `HCR_EL2` -- is this register on a per core level or the setting is valid all the cores? My understanding is that setting HCR_EL2 is only on per core basis.
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<sid-linux>
In general all system registers are on a per core basis rather for the whole system as I understand, correct?
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<sven>
yeah
<sven>
now there are some apple registers that are per cluster instead
<sid-linux>
same for the physical timer register CNTVCT_EL0 -- each core would have its own count i would guess ?
<sven>
and I don’t know the arm arm by heart (yet…? ;)) so there may be architectural ones that are shared as well but I haven’t come across any yet
<maz>
99% of the architected register are per-CPU.
<maz>
things like the system PMU horror *can* be shared.
<maz>
CNTVCT is private as it is influenced by CNTVOFF, which is itself per-CPU.
<sid-linux>
yes that makes sense
<sid-linux>
thanks both !
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<sid-linux>
Question regarding `daif`. If i enter EL2 what is the daif ? (a) The daif when the core was last time in EL2 or (b) the daif of the level you entered _from_ ?
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<maz>
sid-linux: by definition, DAIF are all set to 1 on exception entry, no matter where you enter from.
<maz>
sid-linux: see D1.3.2 in the ARM ARM for all the gory details.
<maz>
(R_WTXBY being the rule relevant to your question)
<maz>
you seem to be missing that PSTATE is saved in SPSR during an exception entry, making (b) irrelevant. (a) cannot happen, as you'd otherwise could get nested exceptions, which the architecture can't support.
<maz>
(or rather cannot support without SW involvement).