marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<bloom> Is it just me or is iBoot's choice of boot partition on a dual boot system completely random
<Emantor> wdym? AFAICS iBoot bundles the partition & kernel together.
<bloom> I have two partitions, 1 with macOS 1 with m1n1
<bloom> When I hit power on, which boots? macOS or m1n1?
<Emantor> For me, it always boots m1n1.
<Emantor> The primary boot system should be configurable from 1TR.
<Emantor> Looks like the information is stored in the nvram as "boot-volume", not sure if thats the variable used by iBoot to device what to boot, but sounds like it.
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<sven> mine also always boots m1n1
<bloom> related - order of the partitions in 1tr
<sven> just sometimes with the annoying startup sound and sometimes without
<Emantor> Interestingly I can't seem to finde the first two UUIDs in the colon separated boot-volumes list.
<Emantor> But the last one points to the "Linux" partition, which in turn had the kernel replaced by m1n1.
<Emantor> sven: There is a "StartupMute
<Emantor> " variable in nvram
<Emantor> I turned it off in macOS and haven't heard the chime since, my nvram value is %01
<Emantor> Yep, setting this to %00 gets the chime back. So you'll want to run "nvram StartupMute=%01" in 1TR to disable it.
<sven> oh.. that sounds useful.
<sven> now i just have to wait until that chime annoys me enough to connect a keyboard/mouse/screen to the mac mini again and fix that :>
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<sven> jannau: you played with the usb pd chip a little bit, didn't you? i rebased my old i2c patches (https://github.com/AsahiLinux/linux/commits/i2c/dev) and hacked the interrupt but the bits i see in IntEvent are strange
<sven> have you mmiotraced those IntEvent registers while mac os was running?
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<jannau> sven: didn't look at the register values, let me capture some traces
<sven> ok. would be interesting to see the whole communication with that chip i think
<sven> they might've redefined the meaning of some of the irq bits :/
<marcan> bloom: order of partitions in 1TR does seem to be random
<marcan> but you can certainly set the default in 1TR
<jannau> sven: https://gist.github.com/jannau/11bd30b329a9d5c19630e6814a8b587d, irq doesn't seem to be correctly disabled though although it should
<jannau> the reads include the byte with the length
<sven> I2C[63]: R[0x14].10 0x0b 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00
<sven> i'm confused by that line
<sven> so it claims a length of 11 but then only sends 9 bytes of data?
<jannau> I might be confused
<sven> oh, wait. you parse the length byte?
<sven> so the first byte of the actual reply is 0x0b?
<jannau> yes, I parse the length, so first byte is the first data byte. sorry
<sven> ok. so apple added more interrupts it seems
<jannau> I wonder why IntEvent1 is 10 byte and IntMask1 is only 9
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<jannau> or it partially respects the smbus read length. The protocol in the TRM is not smbus
<jannau> tps65987 trm has 11 byte wide interrupt registers https://www.ti.com/lit/pdf/slvubh2
<sven> ohh... nice find!
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<jannau> my i2c tracer might be broken, in m1n1 I read 11 bytes from IntEvent 1/2
<jannau> TPS65987DDK might make sense since it it for USB4
<sven> yeah, they might've used that as a base and added all their custom stuff on top
<jannau> sigh, writing to IntEvent1 doesn't seem to stick
<jannau> maybe, it doesn't like the smbus writes
<jannau> err, the writes are fine.
<bloom> that's write
<jannau> sven: something does not make sense: https://gist.github.com/jannau/5334a649ad4e06e710c36ac18cc679db
<jannau> it looks like apple broke the protocol for certain registers
<jannau> or more like they have a different understanding of the read lengths than the controller
<jannau> so it requests 9 bytes from IntEvent1 but the controller reports it has 11 bytes
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<jannau> so the 0x0b was length byte
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<sven> that's fine though. the host asks for N bytes and the device just replies that it can actually send up to N+M bytes
<jannau> they broken the protocol for writing though. the length field is included in the length
<jannau> clearing IntMask1 works now
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<sven> uh, maybe i'm confused but isn't that how it's supposed to work?
<sven> er wait. yeah, i'm confused.
<sven> i think.
<jannau> the kernel does what the documentation says. write 'len' to data[0] and then append len bytes of payload
<jannau> mac os writes len+1 to data[0]
<sven> yeah, and then it always write 65 bytes :D
<sven> still need to send a patch to fix that
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