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<tnt>
Does anyone know what intel mean by Q Pitch ?
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<austriancoder>
karolherbst: thanks - vec8/vec16 are gone now \o/
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<karolherbst>
nice
<karolherbst>
I've updated my patch, because there were a few corner cases, not sure if you tried the latest version
<karolherbst>
austriancoder: ^^
<karolherbst>
ohh, I guess you did
<karolherbst>
but yeah, they are also all gone on my end
<austriancoder>
karolherbst: pulled your branch about 40 min ago
<karolherbst>
I kinda hate how it's done as it relies on copy_prop not being smart enough to reverse the things...
<karolherbst>
kinda have to sit down and rethink the entire process, but if you are e.g. before io lowering, you still have vec8/16 derefs and we can't split them up... or if the vec4 is based on anything else which is still a vec8 copy prop might reverse it
<karolherbst>
like imagine you have hardware which can do a vec16 load (like if your loads are actually byte based and you can do a 16 byte load, vec1x16)
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<DavidHeidelberg[m]>
zmike: it seems like downloaded traces not matching checksum, pretty happy to see that it works sometimes. Otherwise it would run the trace and probably generated incorrect screenshot due to damaged trace. But yes - no logging for piglit.
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<zmike>
DavidHeidelberg[m]: not sure exactly what that means?
<zmike>
why did it crash
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<DavidHeidelberg[m]>
zmike: the downloaded file doesn't match the checksum provided by S3, so the file was (probably) damaged
<DavidHeidelberg[m]>
this shouldn't usually happen, maybe some corruption of filesystem on runner
<DavidHeidelberg[m]>
zmike: the "crash" here is only wait to communicate here, because it's not fail, pass or timeout
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<zmike>
ahh ok
<zmike>
also would it be possible to change the output to not have the ' at the end of the problems.html link
<DavidHeidelberg[m]>
zmike: I have it in not-yet-merged MR :D
<DavidHeidelberg[m]>
I got pissed by it few times already :P
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* DavidHeidelberg[m]
sneaked the commit into 6.4 kernel uprev, but there was some fighting with Cheza boards in the last minute before merge :)
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<zmike>
it's always bothered me
<zmike>
but not enough to do anything about it
<zmike>
DavidHeidelberg[m]: also have you had time to look at that blender trace?
<DavidHeidelberg[m]>
zmike: would you mind make the trace performance-testing compatible? (3x2 frames)? I checked, it works for me, but crashes iris when I try to replay it in perf mode)
<DavidHeidelberg[m]>
if I dropped last frame (which probably does some cleaning) I think it would work
<DavidHeidelberg[m]>
s/3x2/initial frame + 3x2)
<zmike>
so...7 frames?
<DavidHeidelberg[m]>
yup
<DavidHeidelberg[m]>
previous Blender traces didn't work reliably in performance testing, but maybe recent Blender builds will be better
<zmike>
ok updated
<DavidHeidelberg[m]>
nice, look good. loop=1500, no extra memory consumption, 33 fps on Intel.. so far so good
<DavidHeidelberg[m]>
hehe, 150 runs 60 fps.. I think I need improve my laptop cooling :D
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<karolherbst>
gfxstrand: I got told, that for Vulkan SPIR-V it's technically valid to use vec8 and vec16? I was kinda under the impression it's all vec4 at most.
<zmike>
I'm not sure the first part of that is accurate
<zmike>
vec16 is only legal with the Kernel cap, and that cap is not legal in vulkan afaik
<zmike>
vec8 is a bit more nebulous, but I imagine if you try to use a vec8 somewhere then vvl will tell you why you can't
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<karolherbst>
nah, it's actually in the spir-v spec, it's just a bit hidden :D
<karolherbst>
"Vector types must be parameterized only with 2, 3, or 4 components, plus any additional sizes enabled by capabilities."
<zmike>
yes
<zmike>
that's not hidden
<zmike>
and Vector16 requires the Kernel cap
<zmike>
Vector8 doesn't seem to exist in the base spirv spec
<karolherbst>
well.. you won't find it if you search for "OpTypeVector" :D
<karolherbst>
well..
<zmike>
sounds like someone needs to improve their spec-fu
<karolherbst>
Vector16: Uses OpTypeVector to declare 8 component or 16 component vectors.
<alyssa>
given that we've sunsetted the g52 vk experiment (and would remove the code from tree if not for $politics), it really shouldn't be a premerge job imho
<alyssa>
(It has 0 users and, unless I'm very mistaken, is not being developed.)
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<zmike>
careful, those sound like the words of a panfrost developer
<DavidHeidelberg[m]>
Give me numbers or links:) i'll try to look at it today :)
<alyssa>
I don't understand why the job is running in pre-merge at all, the driver is not shipped and not intended to be shipped, it's served its purpose
<alyssa>
frankly i don't know why we have these jobs at all, they're not providing value
<alyssa>
but zmike is right, i'm sounding like a panfrost developer
<alyssa>
I thought we had a simple rule, jobs go into premerge if we expect them to provide significant value, to take 10 minutes or less of execution time not including setup/teardown overhead, and to be robust against flakes
<alyssa>
something like panfrost-g52-vk fails all 3 principles. I dont know why it's there. Adding testing for the sake of adding testing is actively counterproductive.
<alyssa>
and we have a lot of that.
<alyssa>
but i should shut up before i get yelled at again for acknowledging the problems that lots of people are thinking
<alyssa>
so... never mind
<karolherbst>
could send an MR to disable it and then we merge it (or something)
<alyssa>
mesa ci is perfect, please don't punish me again like last time.
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<zmike>
karolherbst: I did some other reviews
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<karolherbst>
cool, thanks
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<DemiMarie>
alyssa: what is the problem with panvk?
<Lynne>
does any hardware offer real 8-component vectors anyway?
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<jenatali>
Fwiw I think the dzn jobs are closer to a 15 minute average, which I was told was fine when deciding what level of fraction to use
<DemiMarie>
And if so, is this specifically the Nvidia problem?
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<robclark>
DemiMarie: given vk's lack of guarantees about undefined behavior, do you _really_ want webgpu enabled without separate sandboxes for the usermode driver?
<DemiMarie>
robclark: what makes desktop Linux different than ChromeOS in this regard, especially with lacros?
<DemiMarie>
the answer to your question is of course “no”, but desktop Linux being inconsistent with ChromeOS is confusing.
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<robclark>
I guess the main difference w/ CrOS is we know what drivers we ship and are in control of uprev'ing them... I'm also not sure what the status of gpu-process sandbox is w/ chrome/ium on desktop linux
<robclark>
(but even in the CrOS case I think we need more hardening)
<DemiMarie>
robclark: If you decided “we don’t support WebGPU with X11 or with non-Mesa drivers” I would support that. It’s the inconsistency that is confusing.
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<robclark>
I don't think x11 really changes much.. as much as the random unknown driver thing.. even with mesa drivers we know what versions we ship and can push out an update... that said, I wasn't involved in this decision wrt. linux vs cros, just speculating
<robclark>
w/ distro linux, it could be some ancient version of mesa, for ex..
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<DemiMarie>
robclark: _insert rant about LTS distros here_
<robclark>
;-)
<DemiMarie>
Simplest solution for the user-space drivers would be to ship Chromium as a Flatpak and use the up-to-date version of Mesa in the relevant runtime.
<DavidHeidelberg[m]>
Demi: that will haunt me in my dreams :D
<DemiMarie>
David Heidelberg: what will?
<robclark>
webgpu haunts me in my dreams
<DavidHeidelberg[m]>
but if I get it right, you can give Chromium flatpak some beta runtime with recent Mesa
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<DemiMarie>
the stable ones do not have recent Mesa? That’s a problem.
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<DemiMarie>
Anyway, I’ll stop so that this does not take away people’s time any more than it has.
<DavidHeidelberg[m]>
I've been told you can somehow use the system ones, just haven't took notes how :D
<DavidHeidelberg[m]>
*system Mesa3D
<DavidHeidelberg[m]>
GPU-Viewer reports 23.1.4
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<robclark>
The real thing would be to have webgl/webgpu canvas's spin off their own private sandboxed gpu-process.. we don't really want usermode part of gpu stack to need to be a security barrier
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<robclark>
(ofc the sandbox thing itself takes a bit of maintenance and sometimes needs to change with mesa versions)
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<DemiMarie>
Should Mesa have its own built-in sandbox?
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<robclark>
I'm not _entirely_ sure how that could work.. I mean if dri_foo.so is dynamically linked against something that hasn't been allowed then we can't even load mesa in the first place.. but there are plenty others who know the mechanics of deploying the sandbox better than I do
<robclark>
usually that sort of thing doesn't change _too_ often so it hasn't been enough of a pain point for CrOS to try to come up with something better.. but as they say, patches welcome ;-)
<austriancoder>
robclark: had you time to have a look at the isaspec doc poc !23763 ? If we could define what information should be shown how I can spend some time on it
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<robclark>
austriancoder: idk if we could generate table, and then example syntax (which might just be dumping the display str w/ instruction name plugged in??).. I think that would be easier to read.. ie:
<gfxstrand>
apteryx: Given that that's obviously a server card, it almost certainly on Linux (they wouldn't be able to sell it otherwise) and probably out-of-the-box.
<gfxstrand>
apteryx: I wouldn't call it a GPU, though.
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<gfxstrand>
It looks like pretty much just a display card.
<airlied>
yeah I've no idea, matrox kinda fail
<airlied>
but a lot of their gpus are now just rebadged other people's gpus
<karolherbst>
apparently it supports GL 2.0 :D
<apteryx>
karolherbst: if it works without proprietary binary firmware blobs, that's already better than AMD!
<karolherbst>
ehhhh....
<karolherbst>
no
<apteryx>
(for my needs)
<karolherbst>
yeah, if you all need a display then yeah.. probably
<gfxstrand>
And D3D9!
<karolherbst>
though I suspect not on linux
<karolherbst>
but also kinda depends on what GPU that actually is
<gfxstrand>
But only Windows 7 and earlier because no WDDM2 (-:
<agd5f>
in the R600 days we actually had a set of shaders and that emulated the old 2D engine. You could actually use the old 2D pm4 packets if you loaded the right state and shaders. not sure if it ever got productized.
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<Lynne>
karolherbst: there's some EU funded project for a custom from scratch GPU using the PPC ISA
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<airlied>
yeah they got distracted into some sort of network accelerator sidetrack as well
<Lynne>
as for risc-v, it's still young, give it time, right now there are no CPUs out that you can buy with the vector extension
<Lynne>
though I do feel like the vector ISA may be a bit too flexible/rigid for a GPU
<Lynne>
they'd have to noop every instruction to set the vector size, and swizzles are afaik not supported
<airlied>
yeah like doing a risc-v gpu should really just be more around the effort of an open isa than reusing the risc-v isa
<airlied>
and creating a gpu/compute isa
<airlied>
that is scalar
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<Lynne>
pretty much all popular RISC ISAs are unsuitable for as a GPU ISA base I think, they all use 32-bit instructions which leaves no room for immediates to allow for swizzles
<Lynne>
x86 may still be the most optimal general purpose ISA to build a GPU ISA around, avx 512 has the right ideas about swizzles via k-registers which most instructions support
<Lynne>
as long as each wavefront has a decently sized uop cache the decoder footprint wouldn't be larger than a CPU's
<karolherbst>
no
<karolherbst>
it's not
<karolherbst>
the best thing about GPUs ISAs are that they are scalar
<airlied>
yeah scalar with subgroup ops seems to be the winner
<karolherbst>
you don't need swizzles
<karolherbst>
so that's a pointless argument against RISC
<Lynne>
really? what about vectors?
<karolherbst>
they don't exist
<karolherbst>
only in memory load/stores
<karolherbst>
thats all
<HdkR>
Vectors are a figment of your imagination~ They can't hurt you anymore~
<ccr>
"there is no spoon."
<karolherbst>
nvidia is purely scalar since nearly forever
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<Lynne>
huh, I was under the impression GPUs had vector units for 4-component float vectors
<karolherbst>
I think pre nv50 is vectorized?
<karolherbst>
Lynne: silly GPUs do
<karolherbst>
but scalar GPU ISAs are always the winner
<karolherbst>
because vectorized ISA are just evidence of wrong mindset
<Lynne>
ah, alright, I stand corrected then, RISC-V is a good base, especially with compressed instructions
<karolherbst>
well
<karolherbst>
no
<karolherbst>
the thing is, that most of the "let's use CPU ISAs on GPUs" miss the point on what makes GPUs fast
<karolherbst>
and it's not the ISA
<karolherbst>
it's the programming model
<karolherbst>
it's a mood point, because running CPUs code on GPUs is a lost battle
<karolherbst>
GPU programming model is fast on GPUs, because parallelism is _implicit_
<airlied>
wish someone would tell that to luxcore :-P
<karolherbst>
like you run a shader per primitive and only think of each primitive of a scalar program
<karolherbst>
and the parallelism happens under the hood
<karolherbst>
in theory you can do great things even with x86 SIMD units, but you won't achieve it if you are using C as your language
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<karolherbst>
because C's programming model maps poorly to GPUs and compilers rely on auto vectorization (which GPUs don't even need)
<Lynne>
so what happened to VLIW GPUs?
<karolherbst>
they are dead
<gfxstrand>
They're a bad idea
<Lynne>
they explicitly specify parallelism
<Lynne>
what replaced them?
<karolherbst>
scalar ISAs
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<Lynne>
oh, I read implicit as explicit
<karolherbst>
ahh, yeah
<karolherbst>
Lynne: anyway, I can recommend reading this series of blog posts: https://pharr.org/matt/blog/2018/04/18/ispc-origins it's not _that_ technical, but it explains the problems pretty well and what's the _actual_ problem
<karolherbst>
in theory you can also make SIMD ISAs work, they are just pointless and have drawbacks you can't really fix
<karolherbst>
at least for GPUs
<airlied>
yeah the auto vectorise story is great
* gfxstrand
looks at Intel's ISA
<gfxstrand>
The "best" SIMD...
<Lynne>
thanks, that looks very interesting
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<Lynne>
why did they split SPIR-V into kernel and non-kernel mode btw? did it have something to do with opencl and silly vector GPUs?
<karolherbst>
llvmpipe even uses the masked SIMD instruction thing described later in the series as well
<karolherbst>
yeah
<karolherbst>
CL is... weird
<karolherbst>
so
<karolherbst>
the main differences are that CL has vec8/vec16 types
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<karolherbst>
and that CL doesn't require a structured CFG
<karolherbst>
everything else being different are just details
<karolherbst>
those are the two major things
<karolherbst>
but you can implement CL just fine on Vulkan SPIR-V
<karolherbst>
it's just more work
<HdkR>
gfxstrand: The best SIMD because you have effectively infinite encoding space to fix past mistakes :P
<Lynne>
I still think vectors have a place in GPUs, if you're the type of maniac who hand-writes assembly :)
<karolherbst>
no
<karolherbst>
it just doesn't make sense for GPUs
<karolherbst>
it makes sense for a couple of instructions, but not for general ALU stuff
<karolherbst>
the problem is really, what if you can't make use of the full vector hardware? then it's just wasted silicon with no inherent benefit, as evertyhing is already threaded anyway
<karolherbst>
high end GPUs run like 10k+ threads at once
<HdkR>
Just scale the scalar GPU hardware wider if you need a wider "SIMD" unit :)
<karolherbst>
at which point SIMD just doesn't make a difference
<karolherbst>
the entire GPU is already a huge "SIMD" unit, you just describe what each of those threads do
<karolherbst>
(divergency is bad on GPUs though for this reason)
<Company>
so you're saying the maniacs should code stuff with more threads instead of with more SIMD?
<airlied>
I did wonder if we should just do an enable "some kernel SPIRV" in vulkan, instead of trying to do all the CL stuff
<Company>
like, one thread for each color channel instead of using SIMD for rgba?
<karolherbst>
yeah... but...
<airlied>
find the most interesting ibts, though I suspect the CL extended instruction set is probably a lot of it
<karolherbst>
airlied: though maybe the middle ground is to allow the CL extended instruction set
<karolherbst>
but...
<airlied>
karolherbst: yes that + vec8/16 but definitely structured cfg :-P
<karolherbst>
yeah.. thing is... we can also just handle it in the driver for everybody instead :D
<karolherbst>
not if they would do anything different
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<karolherbst>
GPU optimized libclc might be a good argument
<karolherbst>
but then you can also just write a vk extension adding that instruction set
<karolherbst>
but yeah... we'll see how it turns out
<karolherbst>
I really should upstream rusticl on zink and file for official conformance :D
<karolherbst>
radv is just being a bit annoying with more crashes then anv or lvp
<karolherbst>
*than
<karolherbst>
and running on nvidia is kinda slow for whatever reason
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<alyssa>
karolherbst: ruzticl conformance .. i hope that deprecates clvk >:)
<karolherbst>
heh
<karolherbst>
I'll just try to be conformant before them
<karolherbst>
I think I ignored it for long enough
<karolherbst>
this xdc conformant rusticl on zink?
<alyssa>
>:)
<alyssa>
30 day window, yeah you could make it
<karolherbst>
I don't have _that_ much time
<karolherbst>
but also
<karolherbst>
I think I need to fix like one or two bugs?
<karolherbst>
I'm mostly there
<karolherbst>
there are just annoying things to figure out
<karolherbst>
"Pass 2374 Fails 69 Crashes 11 Timeouts 0" on anv, where 60 fails are CL_FILTER_NEAREST fails, which the conformance test doesn't check at all
<alyssa>
nice
<karolherbst>
so 9 fails and 11 crashes out of 2400
<alyssa>
karolherbst: when you get a chance btw I want to talk CL on M1 >:)
<karolherbst>
radv is causing more issues.. and I manage to crash Nvidia
<karolherbst>
alyssa: I should upstream my branch :D
<alyssa>
we now have ES3.1 class compute/images + working 8-bit/16-bit/64-bit tested against dEQP-VK
<karolherbst>
yeah...
<alyssa>
right now the thing I'm most worried about are float controls
<karolherbst>
I have it all working
<alyssa>
I have no idea if there's flush-to-zero in hardware, if it's always on, never on, if we can control in the driver..
<alyssa>
I'm nervous abut those contractions tests
<karolherbst>
ohh, that's fine
<alyssa>
can't.
<alyssa>
won't.
<alyssa>
shouldn't.
<karolherbst>
you don't need flush-to-zero supported
<karolherbst>
it's entirely optional
<alyssa>
the problem is that our libclc build assumes ftz
<alyssa>
and I don't want to sign up for building a denorm-aware libclc
<karolherbst>
ohhh...
<alyssa>
for Mali, I had to enable the hardware ftz to pass the contractions tests
<karolherbst>
uhhh...
<karolherbst>
I don't think I had issues with that?
<alyssa>
I know it's not an opencl requirement but I think it effectively is a rusticl one ..
<karolherbst>
yeah.. at this point I don't support denorms yet
<alyssa>
karolherbst: See b261a185508 ("panfrost: Honour flush-to-zero controls on Valhall")
<bnieuwenhuizen>
dcbaker: what happened to 23.2? I see rc2 happened more than 3 weeks ago. Any issues we can help with?
<alyssa>
karolherbst: Presumably, you don't see issues because the float_controls_execution_mode is honoured by the underlying drivers
<karolherbst>
alyssa: mhh.. I can certainly take another look, now that I have working vec8/16 to vec4 lowering
<alyssa>
karolherbst: what's that got to do with anything?
<alyssa>
AGX is scalar
<alyssa>
vec8 stuff gets lowered via alu_width + mem_width
<karolherbst>
not all of it
<karolherbst>
uhh
<karolherbst>
maybe it does now
<karolherbst>
but you were left with some leftoever vec8/16 stuff
<karolherbst>
I never bothered checking actually
<karolherbst>
anyway
<karolherbst>
I have some leftover patches I can submit an MR for
<DavidHeidelberg[m]>
btw. Intel gles + vk StarWars tellusim engine crashes on recent mesa (but I have nightly build without debug). Btw. it worked on stable mesa
<DavidHeidelberg[m]>
I'll compile with debug and drop logs
<karolherbst>
alyssa: though what I really need is a proper agx_get_compute_state_info implementation
<karolherbst>
specifically that `max_threads` property
<kisak>
DavidHeidelberg[m]: file an issue report on gitlab if it hasn't been already so that your findings aren't buried in the backscroll.
<DavidHeidelberg[m]>
kisak: sure sure, I also asked for more update version, if there is any from Tellusim (this is 20221109), anyway still it should work, let me compile one beatiful mesa with intel vk and iris :P
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<alyssa>
karolherbst: should be easy
<alyssa>
In the compiler agx_occupancy_for_register_count gives you the max_threads (grep for it in the src)
<karolherbst>
nice
<alyssa>
so just need to add that to agx_shader_info and then you'll get the value as part of the agx_compiled_shader
<karolherbst>
yeah, that should be good enough
<alyssa>
can't 1000% guarantee correctness but it should be a good enough approximation
<karolherbst>
the CTS will run into issues if that value is too high
<alyssa>
good, I want to hear about those since if I got this wrong, perf will suffer
<illwieckz>
speaking about rusticl on zink, once terakan works, would it be possible to use rusticl on zink to get opencl on terascale?
<illwieckz>
or the vulkan version/features supported would not be enough?
<karolherbst>
uhhh
<karolherbst>
if it supports bda
<illwieckz>
what's bda?
<karolherbst>
real pointers
<illwieckz>
ah ok
<karolherbst>
which I doubt terascale could support
<karolherbst>
not sure
<karolherbst>
you kinda need an MMU for that and all that
<illwieckz>
now that you say it I feel like I already asked and we already had this conversion 🤷♀️️
<karolherbst>
because with CL you can use arbitrary pointers
<karolherbst>
probably
<illwieckz>
the information flows in my brain like if that's not the first time it happened
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<karolherbst>
do gallium drivers expect the frontend to call nir_lower_pack?
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<karolherbst>
at least the glsl linker does it mhhh...
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<karolherbst>
at least zink seems to expect that..
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<Lynne>
airlied: tests passed, but I think someone needs to press the rebase button