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<ayaka_> emersion, where I could send my concern and wish about Allocation Constraints? the dri devel mail list?
<emersion> yeah, probably...
<MrCooper> daniels zmike: FWIW, the container job spuriously passing despite the image push failing should be fixed with current ci-templates upstream
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<dolphin> airlied, sima: drm-intel-gt-next sent, one week later than usual due to the vacations erasing my memory of responsibilities, will still send one next week, hoping to backmerge drm-next early next week to bring in drm-intel-next patches to -gt-next
<dolphin> as a dependency to series on -gt-next by Andi
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<sima> I guess I'll do some drm-next pr wrangling, there's 4 pending
<sima> hm annoying conflicts in amdgpu
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<sima> agd5f_, some amdgpu conflict in your -next pr, please check that I didn't screw up before I add more
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<sima> oops only now noticed the drm-tip conflict, fixing it up
<airlied> oops was that me? sordy
<sima> airlied, nah I think it was me merging the amdgpu-next into drm-next
<sima> that merge also had some conflicts, but now it's -fixes vs -next in amdgpu
<sima> airlied, agd5f_ maybe we want a backmerge if drm-tip looks alright?
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<sima> ok should be fixed now
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<glehmann> how hard would it be for opt_algebraic to support conditions based on multiple source operands? something like (('op1', '#a', ('op2', '#b', 'c')), (replacement pattern), (a & b == 0))
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<alyssa> gfxstrand: i've got a nir patch for you to nak https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24397
<alyssa> i mean, ack
* alyssa sweats
<alyssa> :P
* alyssa should probably check radz
<hakzsam> gfxstrand: any other comments on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416 ?
<pendingchaos> glehmann: probably not too difficult? it could be something like nir_search_helpers, except the function is given variables instead of alu instr
<alyssa> note that nir_search_helpers is a potential shader compile-time problem
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<gfxstrand> hakzsam: Nope. VK patch looks good now
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<alyssa> you wrote that code, I don't know what I'm talking about O:)
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<MrCooper> alyssa: radz being the gen z fork of radv?
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<javierm> sima, pq, emersion: it would be great if you can chime in about https://lists.freedesktop.org/archives/dri-devel/2023-August/417590.html
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<alyssa> MrCooper: sure
<alyssa> it's what i callzink-radv
<alyssa> i've got aliases for all of them
<alyssa> anz, radv, zurnip, azahi
<zmike> pretty sure we agreed on zgxv
<MrCooper> hehe, Freudian slip of radv though
<alyssa> oops
<alyssa> zmike: i thought it was going to be zvzz
<zmike> znv, tz, rzdv, zgxv
<zmike> vowels get out.
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<sima> javierm, I think if DRM_FORMAT_FOO is massively preferred by the hw for reasons, then adding support for DRM_FORMAT_XRGB8888->FOO conversion is ok
<sima> I think all we need to make sure is that in that case XRGB8888 is the very last one in the format list or something like that
<sima> javierm, what I'm really strongly against is if we add funny conversion tricks for anything else than XRGB8888 as input
<sima> since that's just combinatorial explosion madness
<sima> also for these tiny vram gpus we essentially treat the vram as the output hw framebuffer that we manually upload, so *shrug*
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<mripard> sima: it's not even that, there's already support for both RGB888 and XRG8888, but because DMA is so slow it does a memcpy
<sima> javierm, I think when the gem bo was still in vram that would have been a solid case against doing copy tricks for XRGB8888 or so
<mripard> jfalempe patches just makes that memcpy ignores the X component that's going to be ignored anyway
<sima> mripard, I thought the memcpy was because the vram is so limited that we can't really support the full kms api with it's "all the buffers userspace wants" approach?
<mripard> jfalempe was saying that a DMA transfer is slower than a memcpy on most platforms
<javierm> sima: I think so, yeah. Otherwise the driver could use TTM as far as I understand
<mripard> so there might also be due to a size limitation, but it also impacts the performances a lot
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<javierm> sima: we all agree that no other "virtual" format should be exposed but XRGB8888 (and only for compat reasons) but the question here is if is OK for drivers to drop the alpha channel
<javierm> sima: what I suggested jfalempe is to post a patch documented that "only XRGB8888 rule" and also could mention that dropping the alpha channel in the driver for perf reasons could be acceptable
<jfalempe> sima, DMA is 3x to 10x slower on most mgag200 hardware.
<sima> javierm, imo the "only XRGB8888" rule is the important thing
<MrCooper> "drop the alpha channel" doesn't make much sense, since XRGB8888 doesn't have an alpha channel in the first place; the question is whether or not the driver is allowed to use a different format internally
<sima> the "drop the alpha" is imo irrelevant, since whether we upload over spi/i2c or pci bus to the framebuffer memory kinda doesn't matter
<sima> MrCooper, yeah plus that
<sima> mgag200 is essentially like one of these manual upload panel drivers we have plenty of, except the bus is a notch faster than i2c/spi :-)
<javierm> MrCooper: right, I meant drop the X channel (how is that called? opaque channel?) but agree with you that if driver is allowed to convert for perf reasons or not
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<javierm> because AFAIU the only XRGB8888 rule was because user-space has no way if the format exposed is native or not, and so wouldn't have to get a perf hit due format conversions
<javierm> *no way to know
<MrCooper> to me it seems like a no-brainer, the "no implicit format conversion" rule was well-intended but backfires in this case for no benefit I can see
<sima> javierm, jfalempe imo just document that for hw/drivers where XRGB8888 is not support or has a very bad cost in terms of upload/scanout bw it's ok to emulate it in the kernel driver, but _only_ for that format
<sima> MrCooper, I think given how the driver works it still fits without exceptions
<javierm> sima: that's my opinion too. The HW really supports RGB8888 and so the XRGB8888 is "emulated"
<sima> since the driver doesn't expose the actual vram as buffers at all, from a kms pov that's a pure internal implementation detail of the display hw
<sima> javierm, yeah agreed
<sima> like from the overall hw+kms pov the buffer is in system memory and gets scanned out (well manual uploaded) over the pci bus to the display
<sima> aint really any different than uploading with the cpu through some other bus than pci
<sima> the fact that 20 years ago such hw would have been exposed as fbdev video memory directly is kinda irrelevant in todays kms world
<sima> because 20 years ago also a lot more userspace bothered to support RBG888 or at least RGB565, because that was required so much more often
<cedicactus> Maybe, there's no big work needed, maybe you are smarter dunno, but scip has event handler and display connector to controller docs, it has cnf reader and lp translator so tritons bitwuzla is fine for it, not in for working today, but will be dealing with it soon enough.
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<sima> javierm, I think the only clarification we really need is that it's ok to emulate XRGB8888 also in cases where it kinda supported, but just always a terrible choice compared to RGB888
<sima> and so really aside from userspace compat, we really don't want it
* sima shrugs
<javierm> sima: agreed. Thanks a lot for your comments on this!
<sima> in a way by starting to emulate xrgb8888 we've tied our hands a bit, since now even fewer reasons for userspace to support more formats natively for these more oddball display drivers
<sima> but I also think that's still the right pragmatic choice
<javierm> sima: yeah. A prime example is the ssd130x driver whose native format is DRM_FORMAT_R1
<javierm> I don't think that user-space would be interested in supporting monochrome :)
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<javierm> but jokes apart I don't know how much user-space nowadays support RGB888
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<MrCooper> I suspect 0 is a good approximation
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<macromorgan> is there any good way to identify a panel that has no otherwise discernable markings?
<macromorgan> I need a compatible flag for a panel that's basically identical to panel-newvision-nv3051d, but it has different mode flags
<dviola> I wonder if this implies bugs with the host opengl driver rather than virgl: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9321#note_2024534
<dviola> gerddie: thanks for looking into it btw
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<gfxstrand> hakzsam: Wanna trade reviews?
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<hakzsam> sure
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<kallisti5[m]> anyone know if the XOrg Foundation membership gets us PCI-SIG docs?
<kallisti5[m]> I want to look at OCuLink stuff to see how to model our PCI Thunderbolt detection. (aka, IsRemoteDevice or something instead of IsThunderbolt)
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<zmike> alyssa: is there a pass to lower 64bit new-style regs to 32bit?
<pendingchaos> if those regs come from phis, I think there was a pass somewhere for lowering 64-bit phis to 32-bit
<zmike> I've got a pass for it that works fine I was just wondering if there was anything in common
<zmike> I don't think they're exclusive to phis tho
<pendingchaos> (nir_lower_64bit_phis)
<zmike> 👍
<alyssa> yeah nir_lower_64bit_phis
<alyssa> zink should only get regs from phis
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<zmike> that sounds like an adventure for next week's me
<alyssa> gfxstrand: congrats ^_^
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<zmike> 💪
<psykose> congrats!
<psykose> perhaps i won't regret not selling my 1070 during the crypto boom meme, eventually :D
<gfxstrand> Oh, don't worry about selling your 1070. We'll never be able to re-clock those and get anywhere close to decent perf.
<psykose> :D
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