#linux-msm on 2022-01-08 — irc logs at oftc.irclog.whitequark.org

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04:24 <mani_s> CosmicPenguin, qcom platforms in upstream use inbuilt MSI controller in DWC IPs. But the downstream uses the GIC-v3 ITS (if available) for MSI

04:27 <mani_s> I believe the upstream PCI driver is only capable of addressing the MSI's from one endpoint (i.e), connecting a PCIe switch and multiple endpoints won't work

04:27 <mani_s> I've submitted a patch for fixing that: https://lore.kernel.org/linux-pci/20211214101319.25258-1-manivannan.sadhasivam@linaro.org

04:29 <mani_s> I came up with this patch by inspecting the driver only. Not by encountering an issue though

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12:11 <DavidHeidelberg[m]> bamse: Hey! did Sony Xperia T ever booted with mainline? I noticed link to old https://github.com/andersson/kernel/blob/41e99cea7c35e82d74862b0293a24a1930c322c4/arch/arm/boot/dts/sony-blue-mint.dts

12:52 <lumag> mani_s: would this fix an issue with ath11k chips refusing to work if pme has taken one of MSI interrupts?

12:54 <mani_s> lumag, no that's not related. iirc, current ath11k stack uses shared MSI for allocating the interrupts

12:56 <lumag> Well, 32 MSIs per controller, that is the current limit, you seems to be lifting. I had the same issue with ath11k on 8450, which we had on rb5

12:58 <mani_s> lumag, my patch increases the number of endpoint that could be connected. But MAX_MSI_IRQS_PER_CTRL is still 32

12:59 <mani_s> that's the limitation of inbuilt MSI controller

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