10:21 <minecrell> anholt: hm, looks like it's fixed now? :D https://gitlab.freedesktop.org/gallo/mesa/-/jobs/17651707

20:41 <aka_[m]> Do anyone know what is a purpose of multiple PHY_CONTROL_COMMONX regs in 28nm femtophy?

20:41 <aka_[m]> Driver alone seems to only touch one which is defined at too so 0 one but "magic" sequences seems to touch multiple different regs and one for this modem and 8976 touch PHY_CTRL_COMMON2

20:41 <aka_[m]> s/too/top/

20:45 <Mis012[m]> aka_: I wonder if those are DWC's registers or qcom's modifications

20:45 <Mis012[m]> eh, synopsys' I mean

20:46 <Mis012[m]> designware docs might be less unobtanium

20:46 <aka_[m]> Mis012: hmm

20:47 <aka_[m]> maybe USB_PHY_HS_PHY_CTRL_COMMON is just one bigger register

20:47 <aka_[m]> which is split

20:47 <aka_[m]> and takes care of separate functions

20:47 <Mis012[m]> sus

20:47 <Mis012[m]> why would you be splitting registers

20:47 <aka_[m]> 1 seems to be controlling PLL itself

20:48 <aka_[m]> *0

20:48 <aka_[m]> 1 looks like dealing with OTG

20:48 <aka_[m]> 2 related to power supply/clocks

20:49 <Mis012[m]> I wanted to go to sleep...