<z3ntu>
bryanodonoghue: So I guess any SoC with dedicated MIPI_CSI*_CLK_* pins uses clock-lanes = <7>? On older SoCs with MIPI_CSI*_LN0-4 (e.g. msm8974) we had clock-lanes = <1> and data-lanes = <0 2 3 4>
Danct12 has quit [Read error: Connection reset by peer]
travmurav[m] has joined #linux-msm
Danct12 has joined #linux-msm
felixwither[m] has joined #linux-msm
<bryanodonoghue>
it could well be on the older SoCs you can select which pin is the clk alright
<bryanodonoghue>
"gen2" which doesn't indicate any generation that I can discern has a fixed clock pin
vknecht[m] has joined #linux-msm
minecrell[m] has joined #linux-msm
telent has quit [Quit: Ping timeout (120 seconds)]
telent has joined #linux-msm
nergzd723 has joined #linux-msm
Adrian[m]1 has joined #linux-msm
marvin24_ has joined #linux-msm
marvin24 has quit [Ping timeout: 480 seconds]
pespin has quit [Remote host closed the connection]