<aka_[m]>
<aklimov> "aka_: sorry for delays from my..." <- i don't really understand interconnection between these but it looks like there are few "ports" like INT0 INT1 INT2 and these each can have muxed-in RXs
<aka_[m]>
But now how mapping is between rx-macro INTs<->Soundwire<->WCD
<aka_[m]>
qcom,swr-port-mapping seems to contain something but if there is rx0-rx5 then there could be 6 ports exposed to soundwire
<aka_[m]>
tho by checking INT stuff it seems RXes are configured well, INT0 takes RX0 and INT2 takes RX1
<aka_[m]>
So if i playback on RX1 shouldn't it enable CLK?
<aka_[m]>
RX0 does
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<aklimov>
aka_[m]: rx_macro could have 6 ports but maybe not all of are connected, just 5 are used
<aklimov>
aka_[m]: which clk? rx-macro internal clk?
<aklimov>
if i am reading it correct, offset 0x480 in rxmacro, then downstream shows that content of that reg is 0x4 during playback and it is the same with mainline kernel
<aka_[m]>
disturbing kinda
<aklimov>
interesting, my dumps don't have 0x24 there
<aklimov>
aka_[m]: so there are ports from rx macro to soundwire and ports on wcd side and this mapping should be set correctly?
<aka_[m]>
no idea tbh how it works with ports
<aka_[m]>
RX also have ports based on dts
<aka_[m]>
and these seems to be same for wcd
<aka_[m]>
so mapping is 1-1
<aklimov>
aka_[m]: and within each port there are "channels" like hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l ?
<aka_[m]>
probably
<aka_[m]>
each port can prob have 2 channels
<aka_[m]>
maybe im connecting wrong ports somehow
<aklimov>
yeah, i am not sure that it is all correct here too
<aklimov>
but what i don't understand that i was told that people verified everything via RX0 to RX0/AIF1/INP2_1 on rx macro and to RX3 on wcd, it works
<aka_[m]>
maybe they have some expensive setups
<aklimov>
maybe time to read downstream DTs and sources to understand how channels/ports map
<aklimov>
aka_[m]: oh, i need to share some debug data with you, i forgot
<aka_[m]>
a39.skl@gmail.com
<aklimov>
yeah, i saw it in ucm files
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