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<brgl> steev definitely but I have one more crease to iron out and it's merge window anyway ATM
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<marc|gonzalez> lumag: thanks, I'll have a close look at apq8096-db820c for HDMI audio
<lumag> marc|gonzalez, at least it knowingly works :-D
<marc|gonzalez> and I probably won't have time for cpufreq before moving on
<marc|gonzalez> what does "it knowingly works" mean?
<marc|gonzalez> lumag: what does "it knowingly works" mean?
<lumag> "I have verified it few months ago"
<marc|gonzalez> OK thanks
<marc|gonzalez> Where is 6.12-rc1? I thought it was supposed to come out Sunday or Monday?
<lumag> marc|gonzalez, -rc1 is two weeks
<marc|gonzalez> So rc7 was Sep 8. Then on Sep 15, Torvalds made 6.11 final instead of spinning an rc8, so the merge window is open from Sep 15 to Sep 29?
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<marc|gonzalez> lumag: I find it confusing that db820c nowhere imports asoc_qcom_lpass_hdmi_dai_ops... This means this code is NOT required for HDMI audio, and thus what is it used for?
<lumag> marc|gonzalez, I think it's for the DP playback. apq8096 didn't have lpass
<lumag> also it well might be that it's only for the ChromeOS cases, they had slightly different TZ / DSP organisation
<konradybcio> 8996 and 8998 should be similar on the audio side
<konradybcio> though 8998 devices shipped with two codecs: 9335 (same as 96( and 9345 (new) or thereabouts
<marc|gonzalez> Maybe I should post the code I have so far? Perhaps someone knowledgeable could spot something missing? (One can dream)
<konradybcio> maybe you can get srinik or krzk to look at it
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<marc|gonzalez> I'll rebase on 6.12-rc1 when it comes out. Should minimize the diffs
<marc|gonzalez> Right now, I'm just chasing shadows...
<marc|gonzalez> ioctl(4, SNDRV_PCM_IOCTL_PREPARE, 0xaaaae5105db0) = -1 EINVAL
<marc|gonzalez> Tracing where that EINVAL is coming from to hopefully figure out what piece is missing
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<aka_[m]> marc|gonzalez: i bet someone was working on 670/660 audio
<aka_[m]> should be kinda similar
<flamingradian[m]> aka_: 670/660 WCD codecs are attached to PMIC, and 845 wcd codec isn't on pm8998
<aka_[m]> he have 8998
<aka_[m]> imma take a look how it looks
<aka_[m]> wcd9335 or wcd8934
<aka_[m]> connected over soundwire master
<aka_[m]> sounds like 8996 scenario to me
<aka_[m]> and even dsp fw is close to it
<aka_[m]> 2.9 or 3.0 not sure vs 2.8 on 8996t
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<Tooniis[m]> <aka_[m]> "connected over soundwire master" <- slimbus
<aka_[m]> right
<aka_[m]> lumag: any specific idea what could be wrong if dpu fails to dpu_plane_atomic_check?
<aka_[m]> it dies on this
<aka_[m]> SDMA not supported for sure
<aka_[m]> and on SSPP_0 which is alocated by fbcon
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<aka_[m]> hmm, it looks like it goes into this rabbit hole on this one
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<lumag> aka_[m], which platform is it?
<aka_[m]> 8953
<lumag> aka_[m], I'm not sure why you end up in that condition.
<lumag> The platform should have max widths set to 2048
<aka_[m]> function logs max_linewidth to it
<lumag> Hmm. The condition seems incorrect. It should be if ((width != width || height != height || MSM_FORMAT_IS_YUV()) && !test_bit && !test_bit) error_out
<lumag> Hm. Or no
<lumag> We shouldn't proceed if there is no SDMA
<lumag> so this one is correct
<aka_[m]> maybe it shouldn't even go inside that first if
<lumag> Which mode are you trying to set?
<lumag> Can you lower the fps?
<lumag> (or clock in the panel definition)
<lumag> Also, let me check, how does it calculate max_core_clk_rate
<lumag> Can you possibly check it in the debugfs?
<aka_[m]> will printk soon
<lumag> thanks
<lumag> If it is less than 400M we might have found the issue
<lumag> aka_[m], you might want to add opp-table to the MDP with the following values: 400M, 320M, 266.67M, 200M, 160M, 80M, 50M.
<lumag> See how it's done on other platforms
<lumag> But it's interesting, we should find a way to work w/o opp tables
<aka_[m]> lumag: _dpu_plane_calc_clk returns 125712000
<aka_[m]> max_mdp_clk_rate:3051
<aka_[m]> both printed as lld
<aka_[m]> longlongdecimal from what i understand
<lumag> 3051 is rofl
<aka_[m]> lumag: wait a sec i think mdp should have opp
<aka_[m]> lemme see
<aka_[m]> lumag: lmao
<lumag> ?
<aka_[m]> i knew mdp had table because it had but on 8976 i upstreamed
<aka_[m]> indeed 8953 has no such
<aka_[m]> imma try bring it up
<aka_[m]> i would use opps from gcc driver
<aka_[m]> so one you said it looks like
<aka_[m]> lumag: even after adding it still fails
<aka_[m]> kms->perf.max_core_clk_rate shows 3051
<lumag> Hmm, are you running arm64 or arm32 userspace?
<lumag> kernel
<aka_[m]> aarch64 everything
<lumag> Hmm. Could you please check how it ends up with such a strange value?
<aka_[m]> in clk debug it shows this as current rate
<lumag> can you please post clk_summary/
<aka_[m]> mdp_clk_src alone is 3051
<aka_[m]> gpll0 has bogus rate
<aka_[m]> of 6103
<aka_[m]> something went down with gcc it seems
<aka_[m]> i should probably reparent on gpll0_early
<aka_[m]> maybe its some post_div fixes?
<aka_[m]> every single post_div pll seems to have wrong rate
<aka_[m]> or custom code in 8953 fork
<aka_[m]> someone with 660 also claims to have some issues with gpll0
<lumag> aka_[m], could you please post the value of the gcc's 0x21000 register? either from gcc itself or via devmem2 0x01821000
<lumag> aka_[m], I *think* a proper fix might be to set .width = 4 for all clk_alpha_pll_postdiv clocks
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