<jernej>
gamiee: I doubt, it's probably the same as with H6, two dies packaged together and just bonded internally
<gamiee>
jernej: ah makes sense, thanks :)
<jernej>
warpme_: both, dcdca and dcdcb, are supplies for CPU
<jernej>
check schematic, they are connected together
<warpme_>
hmm - i understand both are working in tandem for provide higher max. current? Asking as playing with dvfs on h616 i have random kernel traps for any opp >1.2GHz. it's pretends like i.e. vcpu seems to be not regulated?
<apritzel>
warpme_: what does /sys/kernel/debug/regulator/regulator_summary say? Does it adjust the voltage in there at least?
<warpme_>
or i.e. max current supplied by regulators tandem by some reason is too low for cpu freqs >1.2GHz...
<jernej>
apritzel: It seems to me that AXP305 on OrangePi Zero2 is not configured in polyphase mode by resistor
<jernej>
for DCDC A & B
<jernej>
ah, DCDCB doesn't seem to be used, most components are marked NC
<jernej>
warpme_: so you're planning to add everything except audio? :)
<apritzel>
you can't really trust those schematics (and certainly not the BSP DT)
<apritzel>
I only take information from there as hints or starting points for experimentation
<warpme_>
oh. just started to play with some simple things. thermal seems to work but SoC ths reg. values are way too low (which means crazy temps like +160C accordingly to h616 formula from manual. still don't know why. suspect avcc issue). cpu dvfs seems work but opp >1.2G are unstable. gpu dvfs seem reporting to be operational but tested yet...
<apritzel>
warpme_: maybe it's just the OPPs wrong? What's the voltage for 1.2GHz?
<apritzel>
and have you tried if it gets more stable if you increase the voltage slightly?
<warpme_>
apritzel: efuse reports bin0. re: vcpu increase: yes. and this not helps :-(. definitely i need to do more tests here. btw: got working (sort of) ths. and it works with bsp code logic which is CONTRARY to manual formula logic. go figure!
<warpme_>
manual-> h616 user manual
<jernej>
smaeul: IIRC you looked at audio hub, right? I have no idea how it can be implemented properly in mainline
<jernej>
problem is that all I2S controllers in H616 are in audio hub, even for HDMI audio
<smaeul>
jernej: I have not looked at the audio hub in detail. I think that sort of hardware is what DPCM is intended to model
<jernej>
it's annoying that RX and TX FIFOs are own devices and must be connected to I2S or mixer controller
<smaeul>
It sounds better than A64/AC100, where you have to do TDM over an internal I2S interface to get multiple audio streams
<smaeul>
H6 appears to have the same audio hub as the H616
<jernej>
almost
<jernej>
H6 has additional bit if HDMI codec is connected to standalone I2S or I2S in audio hub
<jernej>
this bit is audio hub
<smaeul>
some other SoCs have an "audio hub enable" bit in the I2S/SPDIF regs, but I think this is something different, maybe just sharing the FIFOs between the controllers
<smaeul>
this would make sense in e.g. the D1, where the SRC is inside I2S2 between the FIFO and the wire. You could do hardware loopback between I2S interfaces at different sample rates. The FIFOs would all run at the max rate, but the wire rates could be different
<smaeul>
but maybe there is a hidden crossbar device?
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<smaeul>
D1 has two LDOs controlled by a register in the middle of the audio codec MMIO. They are routed to pads, so they can be used for non-audio purposes (for example, one is used as the LRADC reference supply)
<smaeul>
any suggestions on how to model this in the DT? do I register the regulators from the codec driver? add a child node with a separate driver and compatible? sibling node with a syscon phandle reference?
<smaeul>
I don't really want to require the audio codec driver to be loaded to use the LRADC
<smaeul>
there is another pair of LDOs controlled by a register in the SRAM/system control MMIO. thes are less of a problem because the SRAM driver is always loaded, but it would be nice not to depend on that either