libv changed the topic of #linux-sunxi to: Allwinner/sunxi development - Did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait for an answer! - This channel is logged at https://oftc.irclog.whitequark.org/linux-sunxi
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<gamiee> Hi, if anyone wants cheap SD card to JTAG breakout board, you can buy this adapter https://a.aliexpress.com/_mrees5b
<gamiee> You can desolder the SD card slot, and you will have access to pins where you can solder headers
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<swiftgeek> a. links are dangerous and mess with site settings
<swiftgeek> and this is how it looks like desoldered http://h5ai.swiftgeek.net/JIGs/%C2%B5SD%20breakout/
<swiftgeek> and for once it has proper dimensions
<swiftgeek> unlike flex one that has over 0.9 mm and will not fit in the slot http://h5ai.swiftgeek.net/JIGs/%C2%B5SD%20flex%20extension/ (and many others rigid ones too)
<swiftgeek> My preferred configuration on the rigid PCB one is µSD slot + JST PH2.0 header
<swiftgeek> and i would recommend using FFC connector there if not using flex PCB on target device, to not put too much strain on target slot
<swiftgeek> but they are all shit signal integrity wise i think :D
<swiftgeek> it failed to work at 104MHz :)
<swiftgeek> (µSD spec mentions 0.70mm ±0.10mm)
<gamiee> swiftgeek: Oh, so you made the same! Cool!
<gamiee> On which SoCs you get JTAG working? Also which openocd configs you used?
<swiftgeek> trying to get openocd working instead of t32 is my next step
<swiftgeek> and i will be mostly messing with rockchip/qcom ones
<swiftgeek> for sunxi i don't know exactly yet how to progress on generating SystemRDL files
<swiftgeek> and i'm not in position that would allow me to bother allwinner about it
<swiftgeek> (SVD/PER would be fine too)
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<apritzel> swiftgeek: gamiee: I use this: https://www.sparkfun.com/products/9419
<apritzel> not for JTAG, but for serial
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<apritzel> saves you the desoldering and allows to boot from SD card still
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<gamiee> apritzel: this looks good! Thanks for sharing! Did you tested JTAG on Allwinner?
<gamiee> swiftgeek: rockchip have JTAG exposed on sdcard too?
<swiftgeek> rockchip has only jtag there
<swiftgeek> trace is over display port
<swiftgeek> and uart over usb
<apritzel> gamiee: no, never tried JTAG
<apritzel> with FEL and most of the boards being un-brickable I never felt the need to
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<gamiee> swiftgeek hmm, interesting (I don't know that much about rockchip platform)
<gamiee> apritzel: hmm, well, I was thinking to use JTAG to debug kernel drivers
<apritzel> gamiee: which ones? from the BSP?
<swiftgeek> yeah most SoCs have uart/usb for loading code that are way more efficient than jtag ways
<apritzel> for mainline I get much quicker and more meaningful insight with either printk or tracing
<swiftgeek> on allwinner i have issue where i want to use µSD as rootvol when it dies to the point of requiring jtag
<swiftgeek> A13, where it freezes up when temperature drops too low
<swiftgeek> (below 10°C)
<swiftgeek> and i'm already using OTG for networking
<swiftgeek> i really need a chamber for those tests in different thermal conditions
<MoeIcenowy> I personally did a microSD to JTAG adapter of my own
<gamiee> apritzel: tracing? (I was mostly using only printk)
<gamiee> And I want to debug BSP
<gamiee> Even cedar is almost fully in userland, still it would be cool to have hardware breakpoints
<MoeIcenowy> (the JTAG pinout follows Altera USB Blaster
<apritzel> gamiee: the kernel has a lot of different advanced debugging features: for a start you can use trace_printk(), and it lands in a file (/sys/kernel/debug/tracing/trace)
<apritzel> gamiee: so you don't flood your console, also it's much faster, since it isn't output immediately
<apritzel> gamiee: then you grep on that or copy it and inspect it somewhere else
<apritzel> gamiee: or you use ftrace to follow the flow inside the kernel: https://www.kernel.org/doc/Documentation/trace/ftrace.txt
<gamiee> apritzel: thanks for letting me know
<gamiee> MoeIcenowy: wow, nice! Thanks. BTW, I seen your OpenOCD repos, did you tried JTAG also on other SoCs?
<MoeIcenowy> gamiee: it's quite easy on ARM SoCs
<MoeIcenowy> but I failed totally on D1
<MoeIcenowy> seems that the C906 JTAG interface is proprietary
<MoeIcenowy> gamiee: the zip file in the repo can be just sent to JLCPCB to manufacture (but I think maybe I should add a README to mention that the board should be 0.8mm thick
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<swiftgeek> welp JTAG by itself isn't much
<swiftgeek> MoeIcenowy: what should be 0.8mm ?
<swiftgeek> PCBnew file looks like µSD
<swiftgeek> that would make it 0.7mm ± 0.10mm
<swiftgeek> in spec i have that's a detail A, measurement C1
<swiftgeek> and cards i have (like sandisk) follow that closely
<swiftgeek> simplified spec has it mentioned without ±
<swiftgeek> that contains table with C1
<swiftgeek> still no datasheet for allwinner D1?
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<smaeul> there's a datasheet if you sign up at AW's website. just nobody has bothered to leak it yet :)
<swiftgeek> sign up where?
<gamiee> Allwinner website
<swiftgeek> ... :D
<swiftgeek> i don't see any signup on https://www.allwinnertech.com/
<swiftgeek> > Please fill in English and figures
<swiftgeek> i'm bad with those IQ tests
<swiftgeek> > register.checkLoginNameRule
<swiftgeek> oh so it's asking me for username, great
<swiftgeek> and it stopped responding to my queries now completely :)
<swiftgeek> smaeul: that's more than sign up, that's NDA process
<swiftgeek> and they have sent me password i generated myself in email xD
<swiftgeek> oh D1 doesn't require that?
<swiftgeek> great
<swiftgeek> that's a nasty watermark, it could be way lighter :<
<swiftgeek> i see several JTAGs so i guess one goes to tensilica ip
<swiftgeek> one for RV64 and one for boundary scan
<smaeul> or one for ARM (no prefix), one for DSP (D-), and one for RISCV (R-)
<swiftgeek> there we go
<swiftgeek> :D
<swiftgeek> smaeul: what arm?
<swiftgeek> i don't get hits for either of arm / cortex
<gamiee> There is dual core A7 in D1
<swiftgeek> and block diagram just omits that?
<gamiee> There is other R-series SoC which is same die
<gamiee> Yes
* swiftgeek confused as fuck
<swiftgeek> gamiee: so like D1 is same die as that R-series but disabled arm stuff?
<gamiee> It's enabled most likely
<swiftgeek> i didn't look yet at any MPcore sources yet, would be great to get a feel how that is implemented ...
<swiftgeek> if it's enabled then i'm just confused here
<smaeul> I don't think it's enabled -- none of the R_CPUCFG bits appear to have any effect
<swiftgeek> i mentioned separate jtag for usual boundary scan, coz that's how rk seems to implement it
<swiftgeek> and qcom has it even stranger, muxed over a lot of spaces
<swiftgeek> welp
<swiftgeek> d1_tina_open doesn't have schematic/pcb footprint, where do i file my complaint ? :D
<smaeul> for the SoC itself?
<smaeul> probably because AW is not selling the chips, only the dev board
<swiftgeek> so i can't do anything fun :<
<smaeul> sunxi SoCs with an AR100 have two JTAGs ("JTAG" and "S_JTAG"). those without (H616) have only one.
<swiftgeek> that's a great thing to mention, thx
<swiftgeek> any mention of interconnect IP that is being used?
<swiftgeek> diagrams didn't look like FlexNoC
<swiftgeek> > Figure 3-2 System Bus Tree
<swiftgeek> not sure if that's on purpose
<swiftgeek> or really something different
<smaeul> there are all sorts of acronyms, but nothing specific. some interesting terms are: GMB, L4_CONN, MSI, PSI
<smaeul> from the patches on the LKML, we know that whatever it is, it's not cache coherent
<swiftgeek> they are already licensing flexnoc so that's a bit confusing
<swiftgeek> ok jtag is mentioned on page 74 of that C906 description but it's not something i will understand xD
<swiftgeek> and that chapter looks more like integration guide than use guide
<swiftgeek> (and neither like description of operation)
<swiftgeek> it just brings me here for some reason https://www.aliexpress.com/item/32955466659.html
<smaeul> yeah, T-HEAD are also the C-SKY people
<swiftgeek> :D
<swiftgeek> why i can't just read damn docs/sources xD
<swiftgeek> systemrdl export at least xD
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<swiftgeek> t-head/c-sky definitely produces english docs so that _cn really implies existence of _en variant
<MoeIcenowy> smaeul: I checked, D1 BROM sets PF bank to R-JTAG
<gamiee> smaeul: so second JTAG is for arisc core? Also, is possible to mux JTAG to some other pins?
<swiftgeek> they all appear muxed in datasheet i linked
<swiftgeek> with like 2 possible pin sets
<swiftgeek> NCIS (CSI controller ?) looks the funniest i guess
<swiftgeek> Table 9-24 PE Multiplex Function / Table 9-25 PF Multiplex Function
<swiftgeek> that is probably the most readable there
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<warpme_> smaeul: re: crust on gs1 & PMIC's IRQ specifier: i found it and issue was by my mistake. all works nice with your current crust code. sorry for false report!
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