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gamiee >
You can desolder the SD card slot, and you will have access to pins where you can solder headers
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swiftgeek >
a. links are dangerous and mess with site settings
08:57
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swiftgeek >
and for once it has proper dimensions
09:00
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swiftgeek >
My preferred configuration on the rigid PCB one is µSD slot + JST PH2.0 header
09:01
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swiftgeek >
and i would recommend using FFC connector there if not using flex PCB on target device, to not put too much strain on target slot
09:01
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swiftgeek >
but they are all shit signal integrity wise i think :D
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swiftgeek >
it failed to work at 104MHz :)
09:10
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swiftgeek >
(µSD spec mentions 0.70mm ±0.10mm)
09:27
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gamiee >
swiftgeek: Oh, so you made the same! Cool!
09:27
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gamiee >
On which SoCs you get JTAG working? Also which openocd configs you used?
09:41
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swiftgeek >
trying to get openocd working instead of t32 is my next step
09:42
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swiftgeek >
and i will be mostly messing with rockchip/qcom ones
09:43
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swiftgeek >
for sunxi i don't know exactly yet how to progress on generating SystemRDL files
09:43
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swiftgeek >
and i'm not in position that would allow me to bother allwinner about it
09:44
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swiftgeek >
(SVD/PER would be fine too)
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apritzel >
not for JTAG, but for serial
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apritzel >
saves you the desoldering and allows to boot from SD card still
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gamiee >
apritzel: this looks good! Thanks for sharing! Did you tested JTAG on Allwinner?
10:58
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gamiee >
swiftgeek: rockchip have JTAG exposed on sdcard too?
10:59
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swiftgeek >
rockchip has only jtag there
10:59
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swiftgeek >
trace is over display port
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swiftgeek >
and uart over usb
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apritzel >
gamiee: no, never tried JTAG
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apritzel >
with FEL and most of the boards being un-brickable I never felt the need to
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gamiee >
swiftgeek hmm, interesting (I don't know that much about rockchip platform)
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gamiee >
apritzel: hmm, well, I was thinking to use JTAG to debug kernel drivers
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apritzel >
gamiee: which ones? from the BSP?
11:22
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swiftgeek >
yeah most SoCs have uart/usb for loading code that are way more efficient than jtag ways
11:23
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apritzel >
for mainline I get much quicker and more meaningful insight with either printk or tracing
11:23
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swiftgeek >
on allwinner i have issue where i want to use µSD as rootvol when it dies to the point of requiring jtag
11:24
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swiftgeek >
A13, where it freezes up when temperature drops too low
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swiftgeek >
(below 10°C)
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swiftgeek >
and i'm already using OTG for networking
11:26
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swiftgeek >
i really need a chamber for those tests in different thermal conditions
11:50
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MoeIcenowy >
I personally did a microSD to JTAG adapter of my own
11:59
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gamiee >
apritzel: tracing? (I was mostly using only printk)
11:59
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gamiee >
And I want to debug BSP
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gamiee >
Even cedar is almost fully in userland, still it would be cool to have hardware breakpoints
12:10
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MoeIcenowy >
(the JTAG pinout follows Altera USB Blaster
12:35
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apritzel >
gamiee: the kernel has a lot of different advanced debugging features: for a start you can use trace_printk(), and it lands in a file (/sys/kernel/debug/tracing/trace)
12:36
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apritzel >
gamiee: so you don't flood your console, also it's much faster, since it isn't output immediately
12:36
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apritzel >
gamiee: then you grep on that or copy it and inspect it somewhere else
14:26
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gamiee >
apritzel: thanks for letting me know
14:26
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gamiee >
MoeIcenowy: wow, nice! Thanks. BTW, I seen your OpenOCD repos, did you tried JTAG also on other SoCs?
14:31
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MoeIcenowy >
gamiee: it's quite easy on ARM SoCs
14:31
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MoeIcenowy >
but I failed totally on D1
14:32
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MoeIcenowy >
seems that the C906 JTAG interface is proprietary
14:33
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MoeIcenowy >
gamiee: the zip file in the repo can be just sent to JLCPCB to manufacture (but I think maybe I should add a README to mention that the board should be 0.8mm thick
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swiftgeek >
welp JTAG by itself isn't much
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swiftgeek >
MoeIcenowy: what should be 0.8mm ?
15:29
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swiftgeek >
PCBnew file looks like µSD
15:29
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swiftgeek >
that would make it 0.7mm ± 0.10mm
15:30
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swiftgeek >
in spec i have that's a detail A, measurement C1
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swiftgeek >
and cards i have (like sandisk) follow that closely
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swiftgeek >
simplified spec has it mentioned without ±
15:40
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swiftgeek >
that contains table with C1
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swiftgeek >
still no datasheet for allwinner D1?
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smaeul >
there's a datasheet if you sign up at AW's website. just nobody has bothered to leak it yet :)
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swiftgeek >
sign up where?
16:41
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gamiee >
Allwinner website
16:45
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swiftgeek >
> Please fill in English and figures
16:45
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swiftgeek >
i'm bad with those IQ tests
16:46
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swiftgeek >
> register.checkLoginNameRule
16:46
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swiftgeek >
oh so it's asking me for username, great
16:49
<
swiftgeek >
and it stopped responding to my queries now completely :)
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swiftgeek >
smaeul: that's more than sign up, that's NDA process
17:06
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swiftgeek >
and they have sent me password i generated myself in email xD
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swiftgeek >
oh D1 doesn't require that?
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swiftgeek >
that's a nasty watermark, it could be way lighter :<
17:14
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swiftgeek >
i see several JTAGs so i guess one goes to tensilica ip
17:14
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swiftgeek >
one for RV64 and one for boundary scan
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smaeul >
or one for ARM (no prefix), one for DSP (D-), and one for RISCV (R-)
17:15
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swiftgeek >
there we go
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swiftgeek >
smaeul: what arm?
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swiftgeek >
i don't get hits for either of arm / cortex
17:17
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gamiee >
There is dual core A7 in D1
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swiftgeek >
and block diagram just omits that?
17:17
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gamiee >
There is other R-series SoC which is same die
17:17
* swiftgeek
confused as fuck
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swiftgeek >
gamiee: so like D1 is same die as that R-series but disabled arm stuff?
17:19
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gamiee >
It's enabled most likely
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swiftgeek >
i didn't look yet at any MPcore sources yet, would be great to get a feel how that is implemented ...
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swiftgeek >
if it's enabled then i'm just confused here
17:21
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smaeul >
I don't think it's enabled -- none of the R_CPUCFG bits appear to have any effect
17:21
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swiftgeek >
i mentioned separate jtag for usual boundary scan, coz that's how rk seems to implement it
17:22
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swiftgeek >
and qcom has it even stranger, muxed over a lot of spaces
17:24
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swiftgeek >
d1_tina_open doesn't have schematic/pcb footprint, where do i file my complaint ? :D
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smaeul >
for the SoC itself?
17:24
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smaeul >
probably because AW is not selling the chips, only the dev board
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swiftgeek >
so i can't do anything fun :<
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smaeul >
sunxi SoCs with an AR100 have two JTAGs ("JTAG" and "S_JTAG"). those without (H616) have only one.
17:27
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swiftgeek >
that's a great thing to mention, thx
17:29
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swiftgeek >
any mention of interconnect IP that is being used?
17:29
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swiftgeek >
diagrams didn't look like FlexNoC
17:30
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swiftgeek >
> Figure 3-2 System Bus Tree
17:30
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swiftgeek >
not sure if that's on purpose
17:30
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swiftgeek >
or really something different
17:39
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smaeul >
there are all sorts of acronyms, but nothing specific. some interesting terms are: GMB, L4_CONN, MSI, PSI
17:39
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smaeul >
from the patches on the LKML, we know that whatever it is, it's not cache coherent
17:44
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swiftgeek >
they are already licensing flexnoc so that's a bit confusing
17:47
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swiftgeek >
ok jtag is mentioned on page 74 of that C906 description but it's not something i will understand xD
17:49
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swiftgeek >
and that chapter looks more like integration guide than use guide
17:49
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swiftgeek >
(and neither like description of operation)
17:55
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smaeul >
yeah, T-HEAD are also the C-SKY people
17:56
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swiftgeek >
why i can't just read damn docs/sources xD
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swiftgeek >
systemrdl export at least xD
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swiftgeek >
t-head/c-sky definitely produces english docs so that _cn really implies existence of _en variant
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MoeIcenowy >
smaeul: I checked, D1 BROM sets PF bank to R-JTAG
19:09
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gamiee >
smaeul: so second JTAG is for arisc core? Also, is possible to mux JTAG to some other pins?
19:18
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swiftgeek >
they all appear muxed in datasheet i linked
19:19
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swiftgeek >
with like 2 possible pin sets
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swiftgeek >
NCIS (CSI controller ?) looks the funniest i guess
19:23
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swiftgeek >
Table 9-24 PE Multiplex Function / Table 9-25 PF Multiplex Function
19:23
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swiftgeek >
that is probably the most readable there
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warpme_ >
smaeul: re: crust on gs1 & PMIC's IRQ specifier: i found it and issue was by my mistake. all works nice with your current crust code. sorry for false report!
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