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<ad__>
"OrangePi PC2 board has DRAM with ODT" , it has internal DRAM ?
<ad__>
or just programmable terminators for external sdram ?
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<ad__>
(just out of curiosity)
<ad__>
yocto building (and rebuilding) gives time to study :)
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<jernej>
ad__: OrangePi PC2 has H5 SoC, which has no embedded DRAM
<jernej>
ODT is supported in DRAM PHY
<jernej>
that is standard feature
<jakllsch>
the board has DRAM
<jakllsch>
not the SoC. the statement you quoted didn't say that though..
<apritzel>
smaeul: can you send an update for the TOC0 mkimage? I might be interested in taking both series then ...
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<jernej>
apritzel: there is only one board config, due to which I can't switch to FDTDIR in PXE config
<jernej>
we have only single U-Boot config, for both, PineH64 model A and model B
<jernej>
there are some minor differences between them
<jernej>
actually, I'm not sure why LE supports model A, but I have it
<apritzel>
jernej: I just have model A (only authentic with that patch wire), and nobody could apparently be bothered to send patches for model B yet, it seems
<jernej>
I would rather make same trick as for pine64 (plus), if possible
<jernej>
if not, I can send model B patches, but we are again at DT files issue
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<apritzel>
yeah, not adding another defconfig is warmly welcomed
<apritzel>
but yeah, the DT files ...
<jernej>
but currently I have no clue if there is any defining difference to check in SPL
<apritzel>
yeah, I was wondering this myself already, and I think I had a look in the schematics already, but didn't find anything quickly
<apritzel>
maybe we can probe some GPIOs that are connected to the WiFi module, and check whether they are floating or stay at a fixed level?
<apritzel>
I had some success with that to tell the Pine64-LTS apart from the Pinebook
<jernej>
IIRC there is wifi daughter board for model A
<apritzel>
there is no need for you to spoil my fancy idea ;-)
<jakllsch>
heh
<jernej>
model A has a PCIe slot
<jakllsch>
and some related gpios, iirc
<apritzel>
right, and I think I tried that already, but they are just connected to the slot pins, so can't be distinguished from just floating because they are NC
<jernej>
PCIE_REST_N (PG14) is pulled down
<apritzel>
OK, will try that when I am home
<jernej>
but I'm not sure if this is enough
<apritzel>
does anyone have a model B to check on the other side?
<jakllsch>
H64 model A here
<jakllsch>
no B
<apritzel>
(would just require typing some commands in U-Boot)
<jernej>
yeah, I have both
<jernej>
it's engineering sample, but except PH2, there should be no difference
<jernej>
yeah, it should float
<jernej>
so, what should I check?
<jernej>
if it's floating, there is no guarantee which value I will get (at least not always)
<apritzel>
jernej: but if you configure the pull-down/pull-ups, the level should follow
<apritzel>
if it's fixed on the other end, it should not
<apritzel>
but if it's pulled down externally, it might not work, depending on the resistor value
<jernej>
exactly
<gamiee>
PINE H64 model B owner here
<jernej>
10k pull down
<gamiee>
What I need to check ?
<apritzel>
if any board designer reads here: please spare three GPIOs to encode a board revision ;-)
<jernej>
gamiee: set PG14 to input, set pull up and check you read 1, repeat with pull down
<jernej>
apritzel: internal pull up/down resistance is 100k
<jernej>
that should work imo
<jernej>
10k is much stronger
<apritzel>
I dimly remember trying that already a while ago, but without success
<apritzel>
I will check again later today
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<ad__>
jernej, ok, thanks
<gamiee>
jernej: will try in few secs
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<gamiee>
jernej: `=> gpio input PG14` and result: `gpio: pin PG14 (gpio 206) value is 1`
<gamiee>
(just I didn't found a way how to pull it up)
<jernej>
via devmem :)
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<gamiee>
ah yeah, okay, let me check the registers
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<jernej>
apritzel: I just tested it on model A and it really behaves as there would be no external pull down
<jernej>
alternatively, its resistance is much higher