<smaeul>
that is what I am using, though rc3 is out now
<apritzel>
I understand, but you mentioned a prerequisite is in -rc2?
<apritzel>
typically I would base on -rc1, since that's what's most maintainers use as a base for -next
<apritzel>
Or was that just the latest HEAD at the time? "Rebase on v5.17-rc2 (CCU module support series was merged)"
<smaeul>
right, it was just the latest tag. I generally rebase at every rc to minimize the delta between my patch branches and my working branches
<apritzel>
I see, thanks
<apritzel>
*compiling*
<apritzel>
smaeul: what's the bus clock for the H616 RTC? CLK_R_APB1? Or is there some gate that we don't define yet?
<smaeul>
there is a gate at 0x20c (and we define it already for a100 and d1 :)
<apritzel>
is that just in the H616, or in the H6 as well?
<smaeul>
also technically in the H6
<smaeul>
if we expose it there, we'd have to mark it CLK_IGNORE_UNUSED or CLK_IS_CRITICAL, since we can't change the RTC binding
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<smaeul>
not just for cross-version compatibility, but also because the existing Linux driver does unsafe things with the number of clock references: `init.num_parents = of_clk_get_parent_count(node) + 1;`
<apritzel>
expose as in: mention in the DT, you mean?
<smaeul>
as in register it in the clock driver
<apritzel>
I was just asking because the -r clock driver is shared between H6 and H616, so I would just add the gate there, but only reference it in the h616.dtsi
<apritzel>
ah, I see
<apritzel>
but that should be no problem, since we have separate structs for both SoCs already, so I just put it in sun50i_h616_r_ccu_clks?
<smaeul>
right, just omit it from `sun50i_h6_r_hw_clks` and you will be fine
<apritzel>
what's this SYSTEM_PLL_32K? I see it only mentioned once in the manual, on the RTC page, but cannot find it on the CCU pages
<apritzel>
if I get this correctly, that's "32 kHz clock from the CCU" aka pll-32k, which is now mandatory as per your new binding?
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<apritzel>
smaeul: so I eventually found this "... or 32K divided by PLL_PERI(2X)" in the RTC section of the H616 manual
<apritzel>
however in contrast to the D1 manual there are no gates mentioned (@0xf30) in the CCU registers
<apritzel>
do you know more about this?
<apritzel>
smaeul: and where does this "pad" go to? Is this some (possibly not connected) pin on the die?
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<apritzel>
ah, found it in the datasheet, I guess it's PG10, function 011: "X32KFOUT"
<apritzel>
and that actually provides a clock to the WiFi/BT chip on the OrangePi Zero2
<apritzel>
but 0x3001f30 stays at 0, so no gates, I guess