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<smaeul> apritzel: I think CCU fanout and RTC fanout are completely unrelated, and only the newest chips have CCU fanout with all the bells and whistles like D1
<apritzel> smaeul: ah, I see
<smaeul> I suppose you got your questions figured out already?
<apritzel> yeah, indeed ;-)
<apritzel> resulting in two new patches
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<bauen1> and i've confirmed, that the SPI1 bus now works properly on the h6 (if you make 1-2 code changes), it does peroperly detect my winbond spi flash
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<apritzel> bauen1: in U-Boot?
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<bauen1> apritzel: yes
<apritzel> bauen1: please don't keep those "1-2 code changes" to yourself ;-)
<apritzel> bauen1: and you mean you put a separate SPI flash chip on SPI1 pins for that?
<bauen1> apritzel: yes, i have some W25Q32JV chips around that i hooked up, and `sf probe` recognised them
<apritzel> cool, I am doing the same with the SPI0 pins on the original Pine64, and it can even boot from there
<jernej> apritzel: any comment on my low level init patches for H6 and H616?
<apritzel> jernej: you mean the PRCM updates?
<jernej> yes
<apritzel> did that actually fix anything for you?
<jernej> nothing that I can see, but I don't like having diffs with BSP init, especially for unknown bits
<jernej> resistor calibration is always good to do
<apritzel> yeah, let me have a closer look
<apritzel> jernej: oh, btw, I guess my OPi Zero2 DRAM is busted, can you test https://github.com/apritzel/linux/tree/h616-v10-beta?
<jernej> at least first patch brings some readability
<bauen1> apritzel: https://github.com/bauen1/u-boot/commit/7255bd5f44721d1132ea7ddf4dac1ca2cd48e2f8 is the patch that made it work, perhaphs i'll figure out how to send that to upstream (and clean it up)
<jernej> apritzel: I will
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<jernej> apritzel: RTC doesn't work, I get "rtc is still busy." non stop
<jernej> last time this happened for me on H6, it was malfunctioning 32k clock
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<apritzel> jernej: thanks, I saw the same. I think this was working before (in v9), so something to stare at for tonight
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<apritzel> bauen1: thanks for the link! That looks nasty to get right, but that's just for SPI1 on the H6, right?
<apritzel> I guess we just leave it until we get the fix for free with smaeul's pinctrl patches
<bauen1> apritzel: yes
<bauen1> apritzel: and it might be a good idea to go over the H6 gpio function values again in case there are similiar errors
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<bauen1> but i can't figure out why this tpm won't talk to me, so i'll try to get a linux with some more drivers booted
<bauen1> or rather i think it's now talking over spi to me, something different than 0xff at least but the values make little sense
<apritzel> bauen1: are you using the right SPI mode?
<bauen1> apritzel: yes, SPI Mode 0 as per TPM 2.0 specs, and i've confirmed that the sunxi spi driver is setting it up right
<bauen1> right now i'm trying if the u-boot soft spi driver yields different results
<benettig> apritzel: going to check thunk.h for sunxi-tools now
<benettig> apritzel: by testing Icenowy's thunk you mean to test it for both F1C100s and A20 with spl/uboot command, right?
<apritzel> benettig: yes, just the same one thunk should be good for both
<benettig> apritzel: fine, I'm onit
<benettig> s/onit/on it
<benettig> apritzel: it's crazy
<benettig> apritzel: it works with armv7+ using Icenowy thunk for armv5te and not on armv5te
<benettig> apritzel:
<benettig> I give a try to Icenowy repo as is:
<benettig> apritzel: ok, with her one work on armv5te
<benettig> and on armv7+ too. So now I compare and find the reason
<benettig> apritzel: f1c200s has MMU not enabled by BROM
<apritzel> benettig: good point, but many other SoCs don't have it as well
<benettig> sctlr = aw_get_sctlr(dev, soc_info);
<benettig> if ((sctlr & ~((0x3) << 22 | (0x7 << 11) | (1 << 6) | 1)) != 0x00050038)
<benettig> pr_fatal("Unexpected SCTLR (%08X)\n", sctlr);
<benettig> if (!(sctlr & 1)) {
<benettig> return NULL;
<benettig> pr_info("MMU is not enabled by BROM\n");
<benettig> }
<benettig> apritzel: aaah right
<benettig> let me check with verbose log
<benettig> I'm in debug with gdb
<benettig> I try before with logging to narrow the problem
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<benettig> apritzel: it does work almost perfectly. Only one thing left, in case of f1c100s sunxi-fel doesn't return and hang. But I work on that
<benettig> apritzel: at least it works on A20 and F1C1/200s, didn't try with other SoCs
<bauen1> soft-spi is just giving me even more funny numbers lol
<benettig> apritzel: here is the branch working for both:
<benettig> There is only the hang on spl/uboot execution now I take care of
<bauen1> but at least some register accesses now seem to return "correcter" values, so there might still be something weird with the hardware spi1 on h6 :/
<apritzel> benettig: well, but didn't you report that the other function were working already (with my branch), except the SPL upload (which is actually the main feature)?
<apritzel> so there is no change, actually?
<benettig> apritzel: there is change. The thunk that now is only armv5te arm code
<benettig> apritzel: only when it executes SPL or uboot it hangs on host side, while the target goes on
<benettig> Check the 2 patches ^^^. I didn’t know how to give credits to Icenowy on the one of thunks.
<apritzel> benettig: my thunk was also v5 only as well, used for all, just a different colour
<apritzel> so I was hoping that Icenowy's thunk would fix the SPL issue
<benettig> apritzel: I’ve started from yours, but the problem is that it worked on armv7+ but not on armv5te, while the Icenowy’s one works on both even if it was dedicated to armv5te
<benettig> apritzel: with SPL issue you mean that host hangs after executing spl or uboot?
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<benettig> apritzel: oh damn, sorry, I've realized only now the mess with patches, there is yours for thunk and then the latest with thunks taken from Icenowy.
<apritzel> no worries, you verified the one thing I was after: that just using Icenowy's thunk does not change the SPL problem
<benettig> apritzel: ok :-)
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