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<smaeul> gamiee: jernej: I don't know what has broken in U-Boot. I haven't tried H3 recently. The patches themselves haven't changed, so it must be something upstream.
<smaeul> gamiee: the SCPI-based PSCI code doesn't have any timeout, so if crust is not running, bootm/bootz will hang (that's when U-Boot does PSCI init)
<smaeul> hmm, all of 2022.04-rc1-00149-g7a9618505a, 2022.04-rc1-00353-g63ed470e84, and 2022.04-rc2-00099-g13c2ed78ab work for me with orangepi_plus2e_defconfig. I wonder what's different with your setup
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<smaeul> A100 aka A133 user manual is available here: https://whycan.com/t_7738.html#p73832
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<swiftgeek> i guess F133 is somewhat related https://whycan.com/files/members/5266/F133_User_Manual_V1.0.pdf
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<swiftgeek> oh f133 is the same as d1?
<swiftgeek> hmm, different package for sure
<swiftgeek> and embedded DDR2
<swiftgeek> might be a fun alternative to V3s then
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<swiftgeek> oh and V3x with twice the ram now :D
<swiftgeek> ugh i still need to hunt down symbols/footprints
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<gamiee> smaeul: hello! I used your branch patch/h3-scp (updated 25 days ago), and this one wasn't able to start crust. I will try commits you sent, thanks
<swiftgeek> ugh not sure how to related to here but had to manually fix url
<swiftgeek> those download pages from chip vendors are getting harder and harder to use
<swiftgeek> xD
<swiftgeek> oh cloning git of the wiki was probably easier than guessing xD
<swiftgeek> (and easier than fetching each individual file)
<swiftgeek> whoa, another chip with great amount of integrated DRAM https://whycan.com/files/members/3672/aic800g3_datasheet_v1.4.pdf
<swiftgeek> yeah it has FEL pin so has to be allwinner chip i guess xD
<swiftgeek> would be great if was actually available
<clever> swiftgeek: do the above docs detail how to configure the ddr2 controller?
<swiftgeek> i doubt it even says where they came from
<swiftgeek> (ip cores)
<clever> ah
<clever> ive been trying to figure out what i even have in the rpi soc's
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<clever> ive got source, but i dont really know what i can mess with
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<swiftgeek> awww no new columns here https://linux-sunxi.org/Used_IP_cores
<swiftgeek> but i guess that means we can still expect them to use dwc, at which point i guess umctl2 docs would be relevant? (just guessing)
<clever> got a link to umctl2?
<swiftgeek> welp those would be in synopsys walled garden, so not much for useful links xD
<clever> yeah, google found this
<clever> swiftgeek: any chance you happen to know other source for umctl2? that could be compared against https://github.com/librerpi/rpi-open-firmware/blob/master/firmware/sdram.c ?
<swiftgeek> clever: so you have RPi and trying to improve state of software on it?
<clever> yeah
<swiftgeek> welp, register can be reshuffled a bit by the implementer so it's hard to tell, especially without sources
<clever> yeah, that file is kinda just a big list of magic numbers
<clever> read_mr/write_mr are at least obvious, and match up to public docs
<swiftgeek> i mean like, if you had actual source, then sometimes a particular register name could be a dead giveaway of who is the supplier of IP core
<clever> there is an 0x53 divisor in there, and (19.2 * 0x53)/4 == 398.4, that sounds like the 400mhz clock for the ddr2 bus
<clever> i do have a header definition, that was auto-generated from the RTL
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<jernej> swiftgeek: You should use https with any linux-sunxi.org link, server doesn't redirect automatically. That's known issue.
<jernej> s/link/url/
<jernej> swiftgeek: that aic800g3 looks (almost?) exactly like Allwinner A100, check pdfs on link which smaeul provided a bit earlier
<jernej> so yes, it's rebranded Allwinner SoC for sure
<swiftgeek> > its security certificate expired 132 days ago.
<swiftgeek> xD
<jernej> ah, that's another issue
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