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<smaeul> apritzel: no, I mean CCU + 0xd0c
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<apritzel> smaeul: ah, that one! Yes, that enables writes to those registers, including the start address
<apritzel> but the question remains how to let the core actually run
<apritzel> it looks like there are just the same three PPU domains implemented as in the D1 (judging by reading from those registers)
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<apritzel> so is there a reset bit for the RISC-V hart?
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<smaeul> apritzel: there is gating at CCU + 0xd04, but I don't know of a reset line
<smaeul> apritzel: if you turn off the CPU domain by writing to PD_COMMAND_REG in the PPU, does that kill the ARM CPUs?
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