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<apritzel>
smaeul: MoeIcenowy: so I can access the RISCV_CFG block via FEL, and I read the default values (0x13 for 0x6010010 and 0x2 for +0x1c), but cannot change anything.
<apritzel>
smaeul: thanks for the PPU link, I was looking for those bits in the manual, and was wondering already if they just saved it (because single core only ;-)
<apritzel>
I guess we need at least write access to RISCV_STA_ADD0_REG
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<MoeIcenowy>
apritzel: so it's not possible to write to RISCV_STA_ADD0_REG ?
<MoeIcenowy>
apritzel: BTW I don't know whether T113 will need the I$ hack
<apritzel>
MoeIcenowy: doesn't seem so, I could execute different readl's just fine
<apritzel>
will check SCTLR later
<apritzel>
MoeIcenowy: writes to any RISCv_CFG register don't stick, at least not just from FEL
<apritzel>
also not sure if the PPU helps, if power domain 0 is *the* CPU
<moteen>
tried multiple images for the past few days but kernel fails to boot in most of them
<hramrach>
riscv is risky :p
<moteen>
damn risky building an image for the past 5 days ;-;
<hramrach>
is it underpowered too? H.264 up to 1080p60 or 4Kp24
<hramrach>
did not get into riscv -kind of don't see the point. much worse support than ARM, and while the core might be free the peripherials aren't anyway
<DuClare>
depending on, the core might not be free either