<smaeul>
I have an A33 tablet (no schematic) with some evidence of DCDC3 being the CPU supply. I would be surprised if this tablet didn't follow the reference design, but I would also be surprised if DVFS worked with the wrong supply in the devicetree
<smaeul>
evidence is this line in /sys/class/regulator/dump which matches the DVFS table for the current CPU frequency (1.2 GHz):
<smaeul>
and that I can toggle DCDC3 in system suspend without hanging or breaking resume, but if I leave DCDC3 off, resume fails
<apritzel>
smaeul: interestingly in this very file the regulator-name of reg_dcdc3 is "vdd-cpu" (even though indeed the cpu node points to reg_dcdc2)
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<apritzel>
also U-Boot's Kconfig says: "On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V."
<apritzel>
and with U-Boot setting DCDC3 to 1.2V, and Linux probably never changing this, the CPUs should always get a comfortable voltage, even for the highest frequency
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<apritzel>
so could it be that we indeed change the wrong rail, and the CPU is just somewhat resilient against VDD-SYS changing?
<apritzel>
The A33 Olinuxino schematic says DCDC3 is CPU and DCDC2 is SYS
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<apritzel>
junari: that looks alright, but we need that on the mailing list
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<wens>
apritzel: just looked at the a23 and a33 tablet reference designs, DCDC2 is SYS+GPU, DCDC3 is CPU
<wens>
same for a31 reference design
<apritzel>
wens: so this is then basically a typo in sun8i-reference-design-tablet.dtsi?
<wens>
or misreading the schematic?
<apritzel>
smaeul: can you do some experiments on your tablet to confirm this? Like running at the highest frequency, with DCDC2 at 1.2, but DCDC3 at 1.04V, and waiting for crashes?
<apritzel>
then setting DCDC2 to 1.04V and DCDC3 to 1.2V, and not seeing any crashes?
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